Vinay Kumar

I completed B.Tech in Electronics and Communication Engineering from DCRUST Murthal and M.Tech. in Microelectronics from IIT Bombay. I have taught a wide variety of courses as a faculty member at DTU. I have maintained a good amount of curiosity and a sense of wonder towards learning electronics and computation in general, and VLSI and algorithm design in particular, especially the practical aspects. My current research focuses on Neuromorphic engineering, another fascinating area that integrates computational neuroscience with analog/mixed-signal design.

Assistant Professor, Dept. of ECE, DTU (2021-present)

1. Analog IC Design (PG)
2. Neuromorphic Engineering (PG)
3. Low Power VLSI Design (PG)
4. Linux, Programming, and Scripting (PG)
5. Layout Design and Skills from Analog Perspective (PG)
6. CMOS Analog Integrated Circuits (UG)
7. Semiconductor Device Physics (UG)
8. Linear Integrated Circuits (UG)
9. Algorithm Design and Analysis (UG)
10. Data Structures and Algorithms (UG)
11. Embedded Systems (UG)
12. Control Systems (UG)
13. Analog Electronics (UG)
14. Electromagnetic Theory (UG)

Google Scholar Citations

Journal Publications:

1. S. Dutta, V. Kumar, A. Shukla, N. R. Mohapatra, and U. Ganguly, Scientific Reports 2017.
2. S. Dutta, T. Chavan, S. Shukla, V. Kumar, A. Shukla, N. Mohapatra, and U. Ganguly, “Dynamics, Design, and Application of a Silicon-on-Insulator Technology Based Neuron,” MRS Advances, vol. 3, no. 57–58, pp. 3347–3357, 2018. doi:10.1557/adv.2018.490

Conference Publications:

1. V. Kumar, U. Ganguly, 14th Non-Volatile Memory Technology Symposium (NVMTS), Jeju (South Korea), 2014.
2. V. S. Senthil Srinivasan, B. Das, V. Sangwan, C. Pinto Gómez, M. Oehme, U. Ganguly and J. Schulze, Device Research Conference, 2015.
3. A. Shukla, V. Kumar, U. Ganguly, International Joint Conference on Neural Networks (IJCNN), 2017.
4. Y. Bahuguna, A. Sinha, S. Adhikari and V. Kumar, "32nm CMOS Analog Circuit Implementation of STDP for SNNs," 2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT), Delhi, India, 2023, pp. 1-3, doi: 10.1109/ICCCNT56998.2023.10307793.
5. M. Chauhan, V. Kumar and V. Sangwan, "10 Transistor Low Power CMOS STDP Circuit in GF 180nm PDK," 2025 IEEE 6th India Council International Subsections Conference (INDISCON), Rourkela, India, 2025, pp. 1-5, doi: 10.1109/INDISCON66021.2025.11252159.
6. M. Chauhan, V. Kumar and V. Sangwan, "Ultra Low Power CMOS STDP Circuit in GF 180NM PDK," 2025 International Conference on Information, Implementation, and Innovation in Technology (I2ITCON), Pune, India, 2025, pp. 1-4, doi: 10.1109/I2ITCON65200.2025.11210562.

1. U. Ganguly, S. Dutta, V. Kumar, Application No. 201721027169, The Patent Office Journal No. 05/2019 dated
01/02/2019.

• 8 Modules of NITTT
• FDP on Advanced Pedagogy by NITTT Kolkata and DTU