PROFILE

Dr. Sumit Kale working as an Assistant Professor in the Department of Electronics and Communication Engineering at Delhi Technological University (DTU), Delhi, since July 2020. He earned his Bachelor of Engineering degree from Samrat Ashok Technological Institute, Vidisha, Madhya Pradesh, and completed his Master of Technology in Microelectronics and VLSI Design from Shri G. S. Institute of Technology & Science, Indore, Madhya Pradesh. He obtained his Ph.D. from the PDPM Indian Institute of Information Technology, Design and Manufacturing (IIITDM), Jabalpur, Madhya Pradesh, in 2017.

Dr. Kale has over 10 years of teaching experience at both undergraduate and postgraduate levels and more than 15 years of research experience in nanoscale device simulation and modeling for analog/RF, digital, biosensor, and gas sensor applications. His research interests also include high-speed low-power circuit design, analog-to-digital converters, and GaN High Electron Mobility Transistors (HEMTs) for power electronics applications.

He has supervised numerous B.Tech., M.Tech., and Ph.D. students in both minor and major projects. Dr. Kale has published several research articles in highly reputed peer-reviewed journals and international conferences. He is also an active peer reviewer for various SCI-indexed journals and conferences.

Dr. Kale is a Senior Member of IEEE and the IEEE Electron Devices Society. He has also served as the Principal Investigator for research projects sponsored by ANRF, IHFC–IIT Delhi, and DTU Delhi

For more details, please visit my website: https://sites.google.com/view/dr-sumit-kale

 

PREVIOUS POSITIONS/ EXPERIENCE

  • At present (6th July 2020 - till date) as an Assistant Professor in the Department of Electronics and Communication Engineering, Delhi Technological University, Delhi, India.

  • Three years one month (3rd April 2017 – 1st May 2020) as Senior Assistant Professor in the Department of Electronics and Communication Engineering, Madanapalle Institute of Technology & Science, Madanapalle, Chittoor, A. P., India.  

  • Two years five months (10th Mar 2010 – 10th August 2012) as Assistant Professor in the Department of Electronics and Communication Engineering, TIT Group of Institutes, Bhopal, M. P., India.  

  • Six months (Sep 2009 - Feb 2010) as Assistant Professor in the Department of Electronics and Communication Engineering, Lord Krishna College of Technology, Indore, M. P., India. 

  • Four months (March 2007 - June 2007) as Trainee Engineer in CMC Limited, Bhopal, M. P., India.

TEACHING (COURSES TAUGHT)

Under Graduate

  1. EC419-Memory Design-- Session- Aug-Dec, 2025

  2. EC101-Basic Electronics and Communication Engineering--Session- Aug-Dec, 2024, 2025.

  3. EC-201-Analog Electronics-I--Session-Aug-Dec, 2020. 

  4. EC202-Analog Electronics-II--Session-Jan-May, 2021, 2025. 

  5. EC261-Analog Electronics--Session-Jan-May, 2022, 2023.

  6. EC302-VLSI Design--Session-Jan-May, 2021, 2022, 2023, 2024, 2025, 2026.

  7. MSPH109-Electronics--Session-Aug-Dec, 2021. 

  8. EC204-Digital Design-II--Session-Jan-May, 2022. 

  9. FEC45-Engineering Exploration--Session-Jan-May, 2023.

  10. EC306-Embedded System--Session-Jan-May, 2023. 

  11. CEC417-CAD for VLSI Design--Session-Aug-Dec, 2023.

Post Graduate

  1. UCC502-Research Meathodology and IPR--Session-Jan-May, 2026.

  2. VLS501-Analog IC Design--Session-Aug-Dec, 2020. 

  3. VLS6401-Mixed Signal Design--Session-Aug-Dec, 2020.

  4. VLS6207-Selected Topics in VLSI--Session-Aug-Dec, 2022.

MEMBERSHIPS

  • IEEE Senior Member

  • IEEE Electron Device Society

PUBLICATIONS

International Journals

  1. Sheshmani Yadav, Sonal Singh and Sumit Kale, A Power-efficient Schmitt-trigger integrated Radiation Hardened single-bitline 12T SRAM cell for High Performance applications, Integration, June 2026, 102780, ISSN 0167-9260, DOI: 10.1016/j.vlsi.2026.102780

  2. Sheshmani Yadav, Sonal Singh and Sumit Kale, A Power-Efficient Schmitt-trigger driven 10T SRAM cell for improved delay performance, Physica Scripta, March 2026. DOI: 10.1088/1402-4896/ae5697

  3. Tanvika Garg, and Sumit Kale, Analytical modeling of buffer trap effects on 2DEG density and gate leakage current in p-GaN HEMT at cryogenic temperatures, Micro and Nanostructures, Volume 211, 2026, 208534, DOI: 10.1016/j.micrna.2025.208534.

  4. Amit Agarwal and Sumit Kale, A Novel D-Mode Triple-Layer Cap Recessed-Gate Al0.20Ga0.80N/GaN HEMT for Radio Frequency and Low Noise Applications, Silicon, Dec. 2025. DOI: 10.1007/s12633-025-03486-2

  5. Amit Agarwal and Sumit Kale, A Novel Depletion-Mode T-shaped Recessed-Gate GaN HEMT with AlGaN/GaN/InAlGaN Double Heterojunction for RF and Low Noise Applications, Micro and Nanostructures, Nov. 2025. DOI: 10.1016/j.micrna.2025.208470

  6. Danishk Barwa, Dhruv Khanna, Harshit Parihar, Sumit Kale, A Novel n+ Pocket Doped L-Shaped Channel TFET for Biosensing Applications, ECS Journal of Solid State Science and Technology, Apr. 2025.  DOI: 10.1149/2162-8777/adccf8

  7. Shashi Ranjan Upadhyay, Sumit Kale, and Anukul Pandey, Dielectric Modulated InAs Pocket Heterojunction Tunnel FET for Biosensor Applications, ECS Journal of Solid State Science and Technology, Mar. 2025. DOI: 10.1149/2162-8777/adc338

  8. Anil Kumar and Sumit Kale, Analytical Modeling of Silicon Nanowire Dielectric Modulated Reconfigurable FET Biosensor, ECS Journal of Solid State Science and Technology, Nov. 2024. DOI: 10.1149/2162-8777/ad8c7e
  9. Tanvika Garg and Sumit Kale, Recent Developments, Reliability Issues, Challenges and Applications of GaN HEMT Technology, IEEE Electron Device Reviews, Nov. 2024. DOI: 10.1109/EDR.2024.3491716
  10. Vijay Thakur, Anil Kumar, and Sumit Kale, Numerical modeling and performance analysis of underlap gate cavity-integrated reconfigurable silicon nanowire Schottky barrier transistor biosensors, Applied Physics A, Oct. 2024. Impact Factor- 2.5 DOI: 10.1007/s00339-024-08010-8
  11. Anil Kumar, Vijay Thakur, Suraj Kumar, Sumit Kale and Kautubh Ranjan Singh, Sensitivity Investigation of Underlap Gate Cavity-Based Reconfigurable Silicon Nanowire Schottky Barrier Transistor for Biosensor Application, Silicon, August 2024.  Impact Factor- 3.4 DOI: 10.1007/s12633-024-03125-2
  12. Anil Kumar and Sumit Kale, Noise and sensitivity analysis of the dielectric modulated reconfigurable SiNW-SBT for biosensor applications, Micro and Nanostructures, Elsevier, July 2024. Impact Factor- 3.1. DOI: 10.1016/j.micrna.2024.207923
  13. Vijay, Anil Kumar and Sumit Kale, Analytical modeling of spacer-engineered reconfigurable silicon nanowire Schottky barrier transistor for biosensing applications,  Micro and Nanostructures, Elsevier, Feb. 2024. Impact Factor- 3.1. DOI: 10.1016/j.micrna.2024.207799
  14. Tanvika Garg and Sumit Kale, Optimization of structural parameters in Omega(Ω)-Shaped gate p-GaN mis-HEMT for performance improvement, Micro and Nanostructures, Elsevier, Feb. 2024. Impact Factor- 3.1 DOI: 10.1016/j.micrna.2024.207793
  15. Anil Kumar and Sumit Kale, Spacer-Engineered Reconfigurable Silicon Nanowire Schottky Barrier Transistor as a Label-Free Biosensor, Silicon, Springer, Dec. 2023. Impact Factor- 3.4
  16. Tanvika Garg and Sumit Kale, A Novel Stepped AlGaN Hybrid Buffer GaN HEMT for Power Electronics Applications, Microelectronics Reliability, Elsevier, Sep.  2023.  Impact Factor- 1.6
  17. Tanvika Garg and Sumit Kale, A Novel p-GaN HEMT with AlInN/AlN/GaN Double Heterostructure and InAlGaN Back-Barrier, Microelectronics Reliability, Elsevier, April 2023.  Impact Factor- 1.6
  18. Anil Kumar and Sumit Kale, A Comparative Analysis of Cavity Positions in Charge Plasma Based Tunnel FET for Biosensor Application, IETE Journal of Research, March 2023.  Impact Factor- 1.87
  19. Prashanth Kumar, Papanasam Esakki, Lucky Agarwal, Pedda Krishna, Sumit Kale, and, Brinda Bhowmick, Recent Progress on Sensitivity Analysis of Schottky Field Effect transistor Based Biosensors, Silicon, Springer, July 2022. Impact Factor- 3.4
  20. Nischit Nagesh Poojari, Rishabh Raj Singh, Nafis Ahmed, and, S. Kale, A Comparative Study of Short Gate and Full Gate Dielectric Modulated Schottky Barrier TFET For Biosensing Application, Silicon, Springer, May 2022. Impact Factor- 3.4
  21. S. Kale, N. K. Hema Latha and, Lokesh K. Bramhane, Design and Proposal of Double Pocket Schottky Barrier TFET with Dielectric Modulation for Biosensors applications, Silicon, Springer, Apr. 2022. Impact Factor- 3.4
  22. Rahul Singh, Shweta Kaim, Rani MedhaShree, Anil Kumar and S. Kale, Dielectric Engineered Schottky Barrier MOSFET for Biosensor Applications: Proposal and Investigation, Silicon, Springer, June. 2021. Impact Factor- 3.4
  23. S. Kale and Madduri Sai Chandu, Dual Metal Gate Dielectric Engineered Dopant Segregated Schottky Barrier MOSFET with Reduction in Ambipolar current, Silicon, Springer, Jan. 2021. Impact Factor- 3.4
  24. S. Kale, Investigation of Dual Metal Gate Schottky Barrier MOSFET for Suppression of Ambipolar Current, IETE Journal of Research, Sept. 2020. Impact Factor- 1.87
  25. N. K. Hema Latha and S. Kale, Dielectric Modulated Schottky Barrier TFET for the Application as Label-Free Biosensor, Silicon, Springer, Dec. 2019. Impact Factor- 3.4
  26. S. Kale, Performance Improvement and Analysis of PtSi Schottky Barrier p-MOSFET Based on Charge Plasma Concept for Low Power Applications, Silicon, Springer, Apr. 2019. Impact Factor- 3.4
  27. S. Kale and P. N. Kondekar, Charge Plasma Based Source/Drain Engineered Schottky Barrier MOSFET: Ambipolar Suppression and Improvement of the RF Performance, Superlattices and Microstructures, Elsevier, vol. 113, pp.799-809, Jan. 2018. Impact Factor- 3.22
  28. S. Kale and P. N. Kondekar, Design and Investigation of Dielectric Engineered Dopant Segregated Schottky Barrier MOSFET With NiSi Source/Drain, IEEE Transactions on Electron Devices, vol. 64, issue 11, pp. 4400-4407, Nov. 2017. Impact Factor- 3.22
  29. S. Kale and P. N. Kondekar, Ferroelectric Schottky Barrier Tunnel FET with Gate-Drain Underlap: Proposal and Investigation, Superlattices and Microstructures, Elsevier, vol. 89, pp. 225-230, Jan. 2016. Impact Factor- 3.22
  30. S. Kale and P. N. Kondekar, Design and investigation of double gate schottky barrier MOSFET using gate engineering, IET Micro and Nano Letters, vol. 10, issue 12, pp. 707-711, 2015. Impact Factor- 1.09
  31. S. Kale and P. N. Kondekar, Suppression of ambipolar leakage current in Schottky barrier MOSFET using gate engineering, IET Electronics Letters, vol. 51, issue 19, pp. 1536-1538, Sep. 2015. Impact Factor- 1.3
  32. S. Kale and P. N. Kondekar, Ambipolar leakage suppression in Ge n-channel Schottky barrier MOSFETs, IETE Journal of Research, vol. 61, issue 4, pp. 323-328, Mar. 2015. Impact Factor- 1.87

International/ IEEE Conferences

  1. Sheshmani Yadav, Sonal Singh, Sumit Kale, A low power Schmitt-trigger driven 8T SRAM cell design with lower leakage current using CMOS Technology , 2025 International Conference on Electronics, AI and Computing (EAIC), June 2025. DOI: 10.1109/EAIC66483.2025.11101322

  2. Kapil Pal, Chaitanya Gupta, Sagar Preet Bhardwaj, Sumit Kale and Anil Kumar, Reconfigurable Silicon Nanowire-Based Schottky Barrier Transistor for Hydrocarbon Gas Detection: A Comprehensive Study, 2024 IEEE International Conference on Smart Power Control and Renewable Energy (ICSPCRE), July 2024. DOI: 10.1109/ICSPCRE62303.2024.10674997
  3. Lipi, Anil Kumar, and Sumit Kale, Reconfigurable Silicon Nanowire- Based Schottky Barrier Transistor for pH Sensor: A Comprehensive Study, 2024 IEEE International Conference on Smart Power Control and Renewable Energy (ICSPCRE), July 2024. DOI: 10.1109/ICSPCRE62303.2024.10675062
  4. Anil Kumar and Sumit Kale, Silicon Nanowire-Based Schottky Barrier Transistor for Biosensor Applications, 2024 IEEE International Conference on Smart Power Control and Renewable Energy (ICSPCRE), July 2024. DOI: 10.1109/ICSPCRE62303.2024.10674789
  5. Sachin, Riya, Sahil Soni, Sumit Kale and Tanvika Garg, An Enhancement Mode Double T- Gate Field Plate GaN HEMT for Power Electronics Application, 2024 IEEE Third International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES), April 2024. DOI: 10.1109/ICPEICES62430.2024.10719173
  6. Tanvika Garg and Sumit Kale, A Gaussian Doped p-GaN HEMT for Power Electronics Application, 2024 IEEE Third International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES), April 2024. DOI: 10.1109/ICPEICES62430.2024.10719370
  7. Tanvika Garg and Sumit Kale, A Novel Enhancement Mode GaN HEMT with MIS and p-GaN structure, 9th IEEE International Conference for Convergence in Technology (I2CT), April 2014, Pune, India. DOI: 10.1109/I2CT61223.2024.10543334
  8. Anil Kumar and Sumit Kale, "Dual-k Reconfigurable Silicon Nanowire Schottky Barrier Transistor for Biosensing," 8th IEEE Electron Devices Technology and Manufacturing Conference (EDTM), March 2024, Bangalore, India. DOI: 10.1109/EDTM58488.2024.10511505.
  9. Sumit Kale, Mohamad Jeeshan, Lokesh Bramhane and Prashanth Kumar, "A Novel Dual Cavity Charge Plasma Based Schottky Barrier MOSFET for Biosensing Application," 3rd International Conference Smart Technologies for Power, Energy and Control (STPEC), Dec. 2023. DOI: 10.1109/STPEC59253.2023.10430617
  10. Anurag Ravish and S. Kale, "A NOVEL DOMINO TECHNIQUE TO REDUCE POWER DISSIPATION AND DELAY VARIATIONS," International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT), 2021, pp. 21-27, doi: 10.1109/RTEICT52294.2021.9573843.
  11. Anurag Ravish and S. Kale, A Comparative Analysis of Domino Techniques for Improved Performance, IEEE 2nd International Conference for Emerging Technology (INCET), Belgaum, India. May 21-23, 2021.
  12. S. Kale, S. Banchhor and P. N. Kondekar, Impact of Underlap Channel on Analog/RF Performance of Dopant Segregated Schottky Barrier MOSFET on Ultra-Thin Body SOI, IEEE International Conference on Emerging Trends in Engineering, Technology and Science, pp. 1-5, Thanjavur, Tamilnadu India, 2016.
  13. S. Kale, S. Banchhor and P. N. Kondekar, Performance Study of High-k Gate & Spacer Dielectric Dopant Segregated Schottky Barrier SOI MOSFET, IEEE 2nd International Conference on Electronics and communication system, pp. 1142-1145, Coimbatore, India, 2015.
  14. S. Banchhor, S. Kale and P. N. Kondekar, Influence of Underlap Gate Length on Analog/RF Performance of Pocket Doped Schottky Barrier MOSFET, IEEE 2nd International Conference on Electronics and communication system, pp. 1152-1155, Coimbatore, India, 2015.
  15. S. Kale and P. N. Kondekar, Impact of Underlap Channel and Body Thickness on the Performance of DG-MOSFET with Si3N4 spacer, IEEE 10th International Conference on Electron Devices and Solid-State Circuits, pp. 1-2, Chengdu, China, 2014.

National Journal/Conferences

  1. S. Kale, “A Noble Design of First Order Sigma Delta Modulator”, International Journal of Electronic and Electrical Engineering, Volume 4, Number 3 , pp. 239-248, 2011, ISSN 0974-2174.
  2. S. Kale & R. S. Gamad, “Design of CMOS Comparator for Low Power & High Speed”, International Journal of Electronics & Engineering Research, Vol. 2, No.1, pp. 29 – 34, 2010, ISSN 0975 – 6450.
  3. S. Kale, “Design of Low Power High Speed Comparator for Sigma Delta ADCs”, National conference in Electrical & Electronics Dept. of SIRT Bhopal on 24th -25th April 2009.

BOOKS/BOOK CHAPTERS (IF ANY)

NIL

PATENTS (IF ANY)

  1. Sumit Kale et al. "Reconfigurable Field Effect Transistor (RFET) Biosensor "  Application no. 202411077386, Indian Patent,  Published, 27/12/2024.

  2. Sumit Kale et al. "A SEMICONDUCTOR DEVICE FOR POWER ELECTRONICS APPLICATIONS", Application no. 202511010535, Indian Patent, Published, 07/02/2025. 

HONOURS AND AWARDS (IF ANY)

  • Best Paper Award at the 6th IEEE International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA 2026) held at Amrita Vishwa Vidyapeetham, Bengaluru Campus.

  • Best Student Paper Award in the 8th IEEE Electron Devices Technology and Manufacturing Conference, 2024 (EDTM) held from March 3rd - 6th 2024 in Bangalore, India.

  • Commendable research award 2025 by DTU Delhi.

  • Commendable research award 2024 by DTU Delhi.

  • Commendable research award 2023 by DTU Delhi.

  • Golden reviewer of IEEE Transactions on Electron Devices for the year 2018.

  • MHRD Scholarship for pursuing a PhD

  • MHRD Scholarship for pursuing M. Tech

SPONSORED/CONSULTANCY PROJECTS

1. Reliable and Efficient Reconfigurable FET Integration in Next Generation Mixed Signal Systems 

 Sponsoring Agency- Young Faculty Grant, DTU Delhi.

 Duration- 2025-2027 (Two years)

 Role- Principal Investigator

 Budget: 5 Lakhs

2. Establishment of Co-innovation Centre in Deep Tech Domain 

 Sponsoring Agency- I-Hub Foundation for Cobotics (IHFC) IIT Delhi

 Duratrion: 2025 Onwards (Three Years)

 Role: Co-innovation Mentor

 Budget: 75 Lakhs

3. Remote Access of EDA Tools Access under Chip 2 Startup Programme

Sponsoring Agency- Ministry of Electronics and Information Technology (MeiTY), Govt. of India

Duration: 2024-2029 (Five Years)

Role: Co-chief Investigator

4. Design and Development of Reconfigurable Silicon Nanowire Schottky Barrier Transistors for Biosensor Applications

 Sponsoring Agency- Science and Engineering Research Board, Department of Science and Technology.

 Duration- 2022-2025 (Three years)

 Role- Principal Investigator

 Budget: 29.65 Lakhs

 

START-UPS (IF ANY)

NIL

MOOC COURSES DEVELOPED (IF ANY)

NIL

PROFESSIONAL DEVELOPMENT

Workshop/FDP/Conferences/Guest Lecture Organized

  1. Organizing Chair of 30th International Symposium on VLSI Design and TEST (VDAT) from 20-22 August 2026 organized by Jaypee Institute of Information Technology, Sector 62, Noida, Uttar Pradesh, in colloboration with Delhi Technological University, Delhi.

  2. Coordinator of ONE WEEK FACULTY DEVELOPMENT PROGRAM (Hybrid Mode) on “Recent Developments in Semiconductor Materials, Devices, and Circuits” May 25-29, 2026 organized by Department of Electronics and Communication Engineering in collaboration with Vinod Dham Centre of Excellence for Semiconductor and Microelectronics (VDSemiX), Delhi Technological University, Delhi.

  3. Coordinator of One Day Hands - on Workshop on "SYSTEM-on-CHIP (SOC) DESIGN USING VERILOG” on 26th February 2026 organized by Vinod Dham Centre of Excellence for Semiconductor and Microelectronics (VDSemiX), DTU,  Delhi.

  4. Organizing member of the 3rd National Conference on Social Responsibility of Educational Institutions held on 12th Jan. 2026 by the Centre for Extension and Field Outreach & Human Resource Development Centre, DTU,  Delhi.

  5. Organizing member of the 2nd National Conference on Social Responsibility of Educational Institutions held on 12th Jan. 2025 by the Centre for Extension and Field Outreach & Human Resource Development Centre, DTU,  Delhi.

  6. One-week Faculty Development Program on "Recent Trends in Semiconductor Technology and Chip Design" from 2nd to 7th Dec. 2024 Sponsored By AICTE Training and Learning Academy, Delhi.

  7. One-day online Workshop on "Nanoscale Device and Its Biosensing Applications" on 19th Nov. 2024 at ECE Department, DTU Delhi. Sponsored By SERB DST. 

  8. One-week Faculty Development Program on "Advancement and Challenges in VLSI Design and Nanoscale Devices" from 27th-31st May 2024 at ECE Department, DTU Delhi.

  9. Organizing Secretary of 11th International Conference on MICROELECTRONICS, CIRCUITS AND SYSTEMS (MICRO 2024), from 16th-17th MAY, 2024 by Vinod Dham Centre of Excellence for Semiconductors and Microelectronics (VDCoE4SM), DTU Delhi.

  10. Webinar on "Solar Cell and OLED Modeling and Simulation Using SETFOS S/W " on 15th March 2022 from 11:00 AM to 12:30 PM.

  11. One-week Online Short-Term Training Program on “Emerging Nanoscale Devices, Circuits, and Its Applications” (NANODC-21) during May 10-14, 2021.

Workshop/FDP/Conferences/Guest Lecture Attended

  1. Attended Industrial Training on the "Internet of Things" from 12th June to 26th June 2023 at National Small Industries Corporation (NSIC) Limited, Okhla Industrial Estate, New Delhi.

  2. Participated in Faculty Development Programme (FDP) on "NBA Accreditation Procedure" held from 09th to 11th May 2022,  organized by Delhi Technological University, Delhi, India.

  3. Participated in One-Week Online Faculty Development Program on the theme of “Machine Learning Applications in Signal Processing and Wireless Networks” held on December 20th-24th, 2021, organized by the Department of Electronics and Communication Engineering, Delhi Technological University, Delhi, India.

  4. Participated in two day training program for the newly recruited Assistant Professors of DTU on 29th-30th Nov. 2021 at DTU Delhi.

  5. Participated & completed successfully AICTE Training And Learning (ATAL) Academy Online Elementary FDP on "Nanotechnology for Electronic and Photonic Devices (NanoDev 2021)" from July 12, 2021 to July 16, 2021 at  Punjab Engineering College (Deemed to be University), Chandigarh.

  6. Participated & completed successfully AICTE Training And Learning (ATAL) Academy Online Elementary FDP on "Nano-Sensors" from July 5, 2021 to July 9, 2021 at Indian Institute of Technology Jodhpur.

  7. Participated in one day E -Workshop on “Innovation And Startup Ecosystem Enablers From Region/ State/ National Level” held on June 23, 2021 organized by Department of Electronics & Communication Engineering, Delhi Technological University, Delhi, India.

  8. Participated in one day "Virtual Symposium on Recent Technological Advancement in Wide/Ultra-wide Bandgap Semicondutor Materials, Devices and Applications: A Step Towards Atma Nirbhar Bharat held on 10th April, 2021 organized by BITS Pilani.

  9. One-week FDP on "Recent Trends in VLSI Design" during 22 to 26 June 2020 organized by Lakshmi Narain College of Technology & Science, Bhopal.

  10. Three Day FDP on "Smart Application Development using IOT- Arduino during 17 to 19 June 2020 organized by ECE department of Vaageshwari College of Engineering Karimnagar.

  11. Online Short-Term course on Nanotechnology for Electronic and Photonic Devices (Nanodev-2020) during 15 - 19 June 2020 supported by TEQIP-III and organized by ECE department of Punjab Engineering College, Chandigarh.

  12. Participated in one-week FDP on “VLSI Chip Design Hands on using open source EDA” jointly organized through NKN by Electronics and ICT Academies from 16th to 20th Dec 2019 at Department of ECE, Gyan Ganga Institute of Technology and Science, Jabalpur.

  13. Participated in AICTE sponsored two-week FDP on “Embedded with Wireless for IOT (EW-IoT-2019)”, organized by Department of ECE from 2nd-14th Dec 2019 at Madanapalle Institute of Technology & Science, Madanapalle, A.P.

  14. Completed and certified in twelve-week FDP course on “Microelectronics Devices to Circuits” from Jul-19 to Nov-19 organized by NPTEL branch of Indian Institute of Technology, Roorkee.

  15. Completed and certified in eight-week FDP course on “CMOS Digital VLSI Design” from Feb-19 to Apr-19 organized by NPTEL branch of Indian Institute of Technology, Roorkee.

  16. Participated in two-week FDP on “Digital VLSI Circuit Design” jointly organized through NKN by Electronics and ICT Academies from 3rd June to 12th June 2017 at Department of ECE, National Institute of Technology Warangal.

  17. Participated in “INUP Familiarization Workshop on Nanofabrication Technologies” held at Indian Institute of Technology Bombay, Mumbai from 25th to 27th May 2016.

  18. Participated in National Symposium on “Innovations in Product Design” organized by PDPM Indian Institute of Information Technology Design and Manufacturing, Jabalpur from 11th to 13th May 2015.

  19. Participated in Workshop on “Research Trends in Nanofabrication with TCAD Simulation” (WON- 2013) organized by PDPM Indian Institute of Information Technology Design and Manufacturing, Jabalpur from 25th to 27th May 2013.

Invited Talk/Session Chair

  • Reconfigurable Silicon Nanowire Schottky Barrier Transistor for biosensing application 

  1. Organized by the Department of Electronics and Communication Engineering, NIT Kurukshetra, 4th-8th March 2024.

  2. Organized by the Department of Electronics and Communication Engineering, VIT Chennai, 14th-18th March 2024.

  3. Organized by the Department of Electronics and Communication Engineering, NIT Rourkela, 6th-10th Nov. 2023.

  • Exploration of Schottky Barrier MOSFETs for Biosensing Application 

  1. Organized by Micro and Nano Devices Research Group School of Electronics Engineering (SENSE), Vellore Institute of Technology Chennai Campus 18th-20th Mar. 2023.

  2. Organized by the National Institute of Technology Delhi, 23rd-28th May 2022. 

 

  • Schottky Barrier MOSFETs For Silicon Nanoelectronics 

  1. Organized by School of Electronics Engineering, Vellore Institute of Technology Vellore Campus from  21st – 25th Nov. 2022.

  2. Organized by School of Electronics Engineering (SENSE) Vellore Institute of Technology Chennai Campus during  7th – 11th Jan. 2022.

  3. Organized by the Electronics and Communication Engineering Department, DTU from 27th-31st May 2024.

  • Session chaired in 3rd edition of the International Conference on Power Electronics, Intelligent Control and Energy System (ICPEICES)  from 26 to 28 April at Delhi Technological University, Delhi, India. 

  • Session chaired in 2nd International Conference on Artificial Intelligence and Signal Processing (AISP’22) Organized by School of Electronics Engineering VIT-AP University, Amaravati, Andhra Pradesh, India from 12th –14th February 2022.

ADVISEES

PhD Students

 1. Dr. Anil Kumar, "Design and Simulation of Novel Nano-Scale Devices for Biosensor Applications"--Aug. 2020 to Dec. 2025

  •     Currently working as Assitant Professor in VIT Bhopal.

2. Dr. Tanvika Garg, "Design and Performance Improvement of Gallium Nitride High Electron Mobility Transistors for Power Electronics Applications"--- Aug. 2021 to Dec. 2025

  •   Currently working as Project Associate in IIT Kanpur.

3. Mr. Sheshmani Yadav, "DESIGN AND ANALYSIS OF POWER-EFFICIENT SRAM CELL FOR HIGH-PERFORMANCE APPLICATIONS"

  • Pursuing Aug. 2023 to present

4. Mr. Amit Agarwal, "Design, Investigation and Optimization of Gallium Nitride High Electron Mobility Transistors for RF and low noise applications"

  • Pursuing Aug. 2024 to Present

5. Mr. Sachin Dhariwal

  • Pursuing Aug. 2024 to Present

6. Ms. Pooja Sahu 

  • Pursuing August 2025 – Present
  • Joint Supervisor with Indira Gandhi Delhi Technical University for Women (IGDTUW), Delhi. 

ANY OTHER INFORMATION

 

For more details, please visit my website: https://sites.google.com/view/dr-sumit-kale