Faculty Profile

PROFILE

PREVIOUS POSITIONS/ EXPERIENCE

Govt. Engineering College,Bharatpur

Malaviya National Institute of Technology JaipurJan 2017 to May 2017 · 5 mos

Airports Authority of IndiaJun 2017 to Sep 2017 · 4 mos

Delhi Technological UniversityOct 2017 to Present · 8 yrs 2 mos

TEACHING (COURSES TAUGHT)

Digital Design with HDL

Testing and Diagnosis of Digital Systems

Digital Design -II

Analog Electronics

MEMBERSHIPS

PUBLICATIONS

Publications:

Paper titled “Plagiarism Detection in Polyphonic Music using Monaural Signal Separation” has been selected for publication and poster presentation in INTERSPEECH-2012 conference held in September 9-13,2012|Portland,Oregon.
Paper titled “Comparison of Time Series Similarity Measures for Plagiarism Detection in Music” was selected for poster presentation and publication in INDICON 2015 12th IEEE India International conference held in Dec 17-20, 2015 | Jamia Millia Islamia , New Delhi.
Paper titled “Hardware Design of Dynamic Time Warping Algorithm based on FPGA in Verilog” has been published online in International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE), Vol.4, Issue 2, February 2015.
Paper titled “Hardware Design of Similarity Measures for Time Series based on FPGA in Verilog” has been selected for publication in 2^nd International Conference on “VLSI, Communication and Networks (VCAN-2015)”, April 18-19,2015| Alwar (Rajasthan).
Book Chapter titled “Novel hardware design of correlation function and its application on binary matrix factorization based features” was selected for oral presentation in International Conference on Artificial Intelligence: Advances and Applications (ICAIAA-2019) (28-29th June 2019) Organized by RTU, Kota, Poornima College of Engineering, Poornima Institute of Engineering & Technology, Jaipur and JNTU Hyderabad, eBook ISBN: 978-981-15-1059-5, Hardcover ISBN: 978-981-15-1058-8, Series ISSN :2524-7565, DOI: 10.1007/978-981-15-1059-5, Publisher: Springer Singapore.
Book Chapter titled “NOVEL FPGA BASED HARDWARE DESIGN OF CANONICAL SIGNED DIGIT MATRIX MULTIPLIER AND ITS COMPARATIVE ANALYSIS WITH OTHER MULTIPLIERS” published in proceedings of ICAIAA 2019 in International Conference on Artificial Intelligence: Advances and Applications (ICAIAA-2019) (28-29th June 2019) Organized by RTU, Kota, Poornima College of Engineering, Poornima Institute of Engineering & Technology, Jaipur and JNTU Hyderabad, eBook ISBN: 978-981-15-1059-5, Hardcover ISBN: 978-981-15-1058-8, Series ISSN :2524-7565, DOI: 10.1007/978-981-15-1059-5, Publisher: Springer Singapore.
P. Garg and K. Suneja, "Hardware design of high speed 1-D DCT module using approximate floating point adder," 2020 7th International Conference on Signal Processing and Integrated Networks (SPIN), Noida, India, 2020, pp. 623-625.
M. Yadav, R. Koul and K. Suneja, "FPGA Based Hardware Design of PCA for Face Recognition," 2020 7th International Conference on Signal Processing and Integrated Networks (SPIN), Noida, India, 2020, pp. 642-646.
A. Gupta and K. Suneja, "Hardware Design of Approximate Matrix Multiplier based on FPGA in Verilog," 2020 4th International Conference on Intelligent Computing and Control Systems (ICICCS), Madurai, India, 2020, pp. 496-498, doi: 10.1109/ICICCS48265.2020.9121004. Publisher: IEEE.
B. Mohindroo, A. Paliwal and K. Suneja, "FPGA based Faster Implementation of MAC Unit in Residual Number System," 2020 International Conference for Emerging Technology (INCET), Belgaum, India, 2020, pp. 1-4, doi: 10.1109/INCET49848.2020.9154105. Publisher:IEEE
R. Koul, M. Yadav and K. Suneja, "Comparative Analysis of FPGA Based Hardware Design of Dynamic Time Warping Algorithm using Different Multiplier Architectures," 2020 IEEE International Conference on Computing, Power and Communication Technologies (GUCON), Greater Noida, India, 2020, pp. 599-603, doi: 10.1109/GUCON48875.2020.9231244.
Jain M., Saini R., Manish, Suneja K. (2020) Novel Hardware Design of Correlation Function and Its Application on Binary Matrix Factorization Based Features. In: Mathur G., Sharma H., Bundele M., Dey N., Paprzycki M. (eds) International Conference on Artificial Intelligence: Advances and Applications 2019. Algorithms for Intelligent Systems. Springer, Singapore. https://doi.org/10.1007/978-981-15-1059-5_13.
A. Negi, D. Saxena and K. Suneja, "High Level Synthesis of Chaos based Text Encryption Using Modified Hill Cipher Algorithm," 2020 IEEE 17th India Council International Conference (INDICON), New Delhi, India, 2020, pp. 1-5, doi: 10.1109/INDICON49873.2020.9342591.
A. Paliwal, B. Mohindroo and K. Suneja, "Hardware Design of Image Encryption and Decryption Using CORDIC Based Chaotic Generator," 2020 5th IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE), Jaipur, India, 2020, pp. 1-5, doi: 10.1109/ICRAIE51050.2020.9358354.
A. Garg, B. Yadav, K. Sahu and K. Suneja, "An FPGA based Real time Implementation of Nosé hoover Chaotic System using different numerical Techniques," 2021 7th International Conference on Advanced Computing and Communication Systems (ICACCS), 2021, pp. 108-113, doi: 10.1109/ICACCS51430.2021.9441923.
A. Kumar, A. Ansari, A. Srivastava and K. Suneja, "Fast Approximate Matrix Multiplier based on Dadda Reduction and Carry Save Ahead Adder," 2021 7th International Conference on Advanced Computing and Communication Systems (ICACCS), 2021, pp. 1058-1061, doi: 10.1109/ICACCS51430.2021.9441960.
Negi A., Saxena D., Kunal, Suneja K. (2022) An Anatomization of FPGA-Based Neural Networks. In: Nayak P., Pal S., Peng SL. (eds) IoT and Analytics for Sensor Networks. Lecture Notes in Networks and Systems, vol 244. Springer, Singapore. https://doi.org/10.1007/978-981-16-2919-8_45.
A. Kumar, M. Kumar, G. S. Jha and K. Suneja, "FPGA based design of multifunction ALU," 2021 Fourth International Conference on Computational Intelligence and Communication Technologies (CCICT), 2021, pp. 72-76, doi: 10.1109/CCICT53244.2021.00025.
Suneja, Kriti & Pandey, Neeta & Pandey, Rajeshwari. (2022). Systematic Realization of CFOA Based Rössler Chaotic System and Its Applications. Arabian Journal for Science and Engineering. 10.1007/s13369-021-06379-9.
A. Chaudhary, A. Kumar, A. Srivastava and K. Suneja, "FPGA-based Pipelined LSTM accelerator with Approximate matrix multiplication technique," 2021 5th International Conference on Electrical, Electronics, Communication, Computer Technologies and Optimization Techniques (ICEECCOT), 2021, pp. 438-442, doi: 10.1109/ICEECCOT52851.2021.9707941.
K. Suneja, N. Pandey and R. Pandey, "OTRA based Design of Chaotic Systems with One and Two Non-Linearities," 2022 International Conference for Advancement in Technology (ICONAT), 2022, pp. 1-5, doi: 10.1109/ICONAT53423.2022.9726005.
B. Yadav, A. Garg, K. Sahu and K. Suneja, "A Real Time FPGA Implementation and Analysis of a Novel Chaotic System," 2022 International Conference for Advancement in Technology (ICONAT), 2022, pp. 1-4, doi: 10.1109/ICONAT53423.2022.9725976.
K. Suneja, A. Chaudhary, A. Kumar and A. Srivastava, "Recent Advancements in FPGA-based LSTM Accelerator," 2022 International Conference for Advancement in Technology (ICONAT), 2022, pp. 1-5, doi: 10.1109/ICONAT53423.2022.9726002.
Suneja, Kriti & Pandey, Neeta & Pandey, Rajeshwari. (2022). Novel Pehlivan–UyarÅglu Chaotic System Variants and their CFOA Based Realization. Journal of Circuits, Systems and Computers. 10.1142/S0218126622501717.
K. Suneja, N. Pandey and R. Pandey, "Realization of Chua’s circuit using VDBA based nonlinear resistor and inductor simulator," 2022 International Mobile and Embedded Technology Conference (MECON), Noida, India, 2022, pp. 367-371, doi: 10.1109/MECON53876.2022.9751973.
K. Suneja, N. Pandey and R. Pandey, "Circuit realization of chaotic systems with quadratic nonlinearity using AD633 based generic topology," 2022 International Conference on Computing, Communication, and Intelligent Systems (ICCCIS), Greater Noida, India, 2022, pp. 284-289, doi: 10.1109/ICCCIS56430.2022.10037747.
S. Suchit and K. Suneja, "Implementation of Secure Communication System Using Chaotic Masking," 2022 IEEE Global Conference on Computing, Power and Communication Technologies (GlobConPT), New Delhi, India, 2022, pp. 1-5, doi: 10.1109/GlobConPT57482.2022.9938303.
Suneja, K., Garg, A., Yadav, B., Sahu, K. (2023). Analysis of Adaptive Control Synchronization of Nosé–Hoover Chaotic System. In: Senjyu, T., So-In, C., Joshi, A. (eds) Smart Trends in Computing and Communications. SmartCom 2023. Lecture Notes in Networks and Systems, vol 650. Springer, Singapore. https://doi.org/10.1007/978-981-99-0838-7_33.
K Suneja, N Pandey, R Pandey, “A Novel Chaotic System with Exponential Nonlinearity and its Adaptive Self-Synchronization: From Numerical Simulations to Circuit Implementation,” Journal of Circuits, Systems and Computers, 2350296.
K. Suneja, B. Kumar, K. Jha and L. S. Chuphal, "Image Encryption Using Novel Chaotic System," 2024 3rd International Conference for Innovation in Technology (INOCON), Bangalore, India, 2024, pp. 1-4, doi: 10.1109/INOCON60754.2024.10511693.
Suneja, K., Pandey, N. & Pandey, R. Novel four dimensional hyperchaotic system: analysis, adaptive control, analog and digital circuit design. Int. j. inf. tecnol. 17, 1137–1145 (2025). https://doi.org/10.1007/s41870-024-02335-6

BOOKS/BOOK CHAPTERS (IF ANY)

PATENTS (IF ANY)

HONOURS AND AWARDS (IF ANY)

START-UPS (IF ANY)

MOOC COURSES DEVELOPED (IF ANY)