PROFILE

Profile:

Dr. Deva Nand currently working as an Associate Professor in the Department of Electronics & Communication Engineering, Delhi Technological University, Delhi, India and have more than 18 years of teaching and research experience. He has published several papers in International Journals of repute and also published several papers in National/International Conferences also. He has been granted two patents and many in queue for publication and grant. His research interests include Analog and Digital CMOS circuit designing, Analog Devices Modeling and Simulation, Digital System Design using HDLs. He is member of BoS/DRC of Deptt. of ECE, DTU. He is member of Vinod Dham Centre of Excellence for Semiconductor and Microelectronics at DTU, Delhi.

PREVIOUS POSITIONS/ EXPERIENCE

Academic Positions:

1. Associate Professor, Deptt of ECE, DTU since 15.01.2022.

2. Assistant Professor, Deptt of ECE, DTU,15.01.2019 to 14.01.2022.

3. Assistant Professor, Deptt of ECE, DTU,15.01.2015 to 14.01.2019.

4. Assistant Professor, Deptt of ECE, DTU,15.01.2010 to 14.01.2015.

TEACHING (COURSES TAUGHT)

Courses Taught:

1. VLSI Design (UG)

2. Digital Design-I (UG)

3. Digital Design-II (UG)

4. Analog Electronics-I (UG)

5. Analog Electrnoics-II (UG)

6. Mixed Signal Design (PG)

7. Analog IC Design (PG)

8. Digital IC Design (PG)

MEMBERSHIPS

Professional Memberships:

•Life time membership of ISTE (LMISTE). ISTE: Membership No. LM-99435
•Member IEEE IEEE: Membership No. 92028016
•IAENG (International Association of Engineers) IAENG: Membership No.177536
•IEEE Circuits and Systems Society (CASS) (No. 92028016)

PUBLICATIONS

Publications:

National Conferences:

  1. Deva Nand, “A systematic study of winner take all circuits” National Conference on Future technologies in science and engineering (FTSE-2011) organized by PDM Group of Institutions, Bahadurgarh, Haryana, India during November 17-18, 2011.

 

International Conferences:

  1. Neeta Pandey, Rajeshwari Pandey, Deva Nand and Abhishek Kumar, “Current mode rectifier configuration based on OFCC” IEEE International Conference on Signal Propagation and Computer technology (ICSPCT-2014) organized by Department of Electronics Instrumentation and control engineering, Govt. Engg. College, Ajmer, Rajasthan during July 12-13, 2014. DOI: 10.1109/ICSPCT.2014.6884960.
  2. Divyesh Sachan, Deva Nand, Neeta Pandey, “Universal Biquadratic Filter using Operational Floating Current Conveyor (OFCC)” 28th International Conference on Microelectronics (ICM-2016), held at Nile University, Cairo, Egypt during December 17-20, 2016, pp. 317-320. DOI: 10.1109/ICM.2016.7847879.
  3. D. Nand, N. Pandey, R. Pandey and S. Jindal, "Operational Floating Current Conveyor based Digitally Controlled Hearing Aid," 2018 5th International Conference on Signal Processing and Integrated Networks (SPIN), Noida, India, 2018, pp. 647-651, doi: 10.1109/SPIN.2018.8474207.
  4. Deva Nand, Neeta Pandey, Manish Harjai, "Voltage Mode Instrumentation Amplifier using Current Mode Block" in International Conference on Materials, Applied Physics & Engineering (ICMAE-2018) held in Indore, M.P. during 3rd-4th June 2018.
  5. Deva Nand, Neeta Pandey, Varun Bhanoo, Ashmin Gangal, “Operational floating current conveyor based TAM & TIM shadow filter” in 4th International Conference on Computers & Management (ICCM-2018) held at G. B. Pant Engineering College, Delhi during 22-23 December, 2018.
  6. Deva Nand, Neeta Pandey, Ashmin Gangal, Varun Bhanoo, “New Shadow filter configuration using OFCC” in 1st International Conference on Signal Processing, VLSI and Communication Engeering (ICSPVCE-2019) held at DTU, Delhi during 28-30 March, 2019.
  7. Deva Nand, Vishwajeet Singh, Jayesh Trivedi, “Voltage mode precision rectifiers based on DXCCII” in 1st International Conference on Signal Processing, VLSI and Communication Engeering (ICSPVCE-2019) held at DTU, Delhi during 28-30 March, 2019.
  8. D. Goel and D. Nand, "VDDDA Based Multifunction Voltage-Mode MISO Filter," 2020 4th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech), Kolkata, India, 2020, pp. 1-6, doi:10.1109/IEMENTech51367.2020.9270071.
  9. Deva Nand, “Single Dual-X Current Conveyor based BASK/BPSK Modulators” IOP Conf. Ser.: Mater. Sci. Eng. 1020 012011. doi:10.1088/1757-899X/1020/1/012011
  10. Sweta Kumari and Deva Nand, “Current-mode Positive and Negative Rectifier based on DDCC suitable for Higher Frequency operations” 2021 IOP Conf. Ser.: Mater. Sci. Eng. 1084, 012079. doi:10.1088/1757-899X/1084/1/012079
  11. Ayush Kumar, Ankit Kumar, Deva Nand, “Design and Study of Dadda Multiplier by using 4:2 Compressors and Parallel Prefix Adders for VLSI Circuit Designs”, 2nd International Conference for Emerging Technology (INCET), Belagavi, India, 21-23 May 2021. doi:10.1109/INCET51464.2021.9456283
  12. Neetika Yadav, Neeta Pandey, Deva Nand, “LCNT incorporated domino with footed diode inverter” 8th International Conference on Signal Processing and Integrated Networks (SPIN), pp. 839-843, 2021.
  13. Deva Nand, Aakash Yadav, Pradeep Kumar, Srinivas Kumar, “Internet of Things Based Energy Harvesting using Piezoelectric Discs” 2021 Asian Conference on Innovation in Technology (ASIANCON), pp. 1-6, 2021.
  14. Dheeraj Singh, Deva Nand, Atul Kumar, “Newly realized grounded capacitance multiplier using single CFDITA” 2021 7th International Conference on Signal Processing and Communication (ICSC), 362-365, 2021.
  15. Neetika Yadav, Neeta Pandey, Deva Nand, “CNTFET based Transmission Gate Diffusion Input Logic (C-TGDI) design” 2021 5th International Conference on Electrical, Electronics, Communication, Computer Technologies and Optimization Techniques (ICEECCOT), pp. 701-705, 2021.
  16. Sweta Kumari, Deva Nand, “DDCC-based MISO type Voltage-mode First-order Universal Filter” 2022 2nd International Conference on Intelligent Technologies (CONIT), pp. 1-6, 2022.
  17. Mudit Agarwal, Mradul Mittal, Milind Gautam, Deva Nand, “Real-Time Facial Emotion Classification using Deep Convolution Neural Network” 2022 2nd International Conference on Intelligent Technologies (CONIT), pp. 1-6, 2022.
  18. A Kaul, S Rewari, D Nand, “Macaroni Channel-Nanowire-Field Effect Transistor (MC-NW-FET) for Gate Induced Drain Leakage (GIDL) Reduction Application”, 2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON), pp. 35-38, 2022.
  19. Neetika Yadav, Neeta Pandey, Deva Nand, “CNTFET Based M-DMTGDI (CMDMTGDI) Design and Its Leakage Analysis” 10th International Conference on Signal Processing and Integrated Networks (SPIN), pp. 515-521, 2023.
  20. Neetika Yadav, Neeta Pandey, Deva Nand, “Energy Efficient Dual Mode DCVSL (DM-DCVSL) design” Second International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT), pp. 1-5, 2023.
  21. Neetika Yadav, Neeta Pandey, Deva Nand, “Energy Efficient CNTFET based Dual Mode Logic (C-DML) Design” Second International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT), pp.1-6, 2023.
  22. S. Suchit, P. Goenka and D. Nand, "Implementation of Secure Communication System using Various Chaotic Systems," 2024 3rd International Conference for Innovation in Technology (INOCON), Bangalore, India, 2024, pp. 1-4, doi: 10.1109/INOCON60754.2024.10511819.
  23. A. Kumar, Ashvin, A. Kumar and D. Nand, "Comprehensive Liver Tumour Detection and Classification of its Stages Using Deep Learning and Image Processing," 2024 IEEE International Conference on Smart Power Control and Renewable Energy (ICSPCRE), Rourkela, India, 2024, pp. 1-6, doi: 10.1109/ICSPCRE62303.2024.10674796.
  24. D. Nand and S. Kumari, "Implementation of TAM-Based Fundamental Analog and Arithmetic Operations Using DDCCTA," 2024 First International Conference for Women in Computing (InCoWoCo), Pune, India, 2024, pp. 1-5, doi: 10.1109/InCoWoCo64194.2024.10863706.
  25. A. Kaul, S. Rewari and D. Nand, "Field Effect Transistor Incorporating Negative Capacitance and Nanowire Structures for the Attenuation of Gate Leakage Phenomena," 2024 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON), Kolkata, India, 2024, pp. 607-611, doi: 10.1109/EDKCON62339.2024.10870658.
  26. S. Gosai, D. Nand, M. Ganesh and S. Rewari, "Junctionless Accumulation Mode Dual Gate Ferroelectric FET (JAM-DG-FE-FET) for High Cut-Off Frequency Applications," 2024 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON), Kolkata, India, 2024, pp. 1-4, doi: 10.1109/EDKCON62339.2024.10870812.
  27. Vijay Thakur; Deva Nand, “Breast Cancer Detection using T-gated Reconfigurable Field Effect Transistor-based Biosensor”, 2025 Devices for Integrated Circuit (DevIC), Kalyani, India, 2025, pp. 358-362. doi: 10.1109/DevIC63749.2025.11012198
  28. S. Yadav, V. Thakur, A. Kaul, A. Das, S. Rewari and D. Nand, "Gallium Nitride Gate-All-Around Macaroni Field Effect Transistor (GaN-GAA-MCFET): Biosensor for DNA detection," 2025 Devices for Integrated Circuit (DevIC), Kalyani, India, 2025, pp. 348-352, doi: 10.1109/DevIC63749.2025.11012312.
  29. A. Kaul, S. Rewari and D. Nand, "Mathematical Modelling of Gate Leakage in Channel Interface Engineered-Electrostatic Potential Modulated Field Effect Transistor for Advanced Digital Applications," 2025 5th International Conference on Electrical, Computer and Energy Technologies (ICECET), Paris, France, 2025, pp. 1-6, doi: 10.1109/ICECET63943.2025.11471702.

 

International Journals:

  1. Pandey, Neeta, Nand, Deva, Khan, Zubair, Single-Input Four-Output Current Mode Filter Using Operational Floating Current Conveyor, Active and Passive Electronic Components, 2013, 318560, 8 pages, 2013. https://doi.org/10.1155/2013/318560 (Scopus)
  2. Neeta Pandey, Deva Nand, Zubair Khan, “Operational Floating Current Conveyor based Single Input Multiple Output Transadmittance mode filter” Arbian Journal of Science and Engineering (Springer), Vol. 39, pp. 7991-8000, 2014. https://doi.org/10.1007/s13369-014-1369-z (SCI)
  3. Neeta Pandey, Deva Nand, Rajeshwari Pandey, “Generalized Operational Floating Current Conveyor based Instrumentation Amplifier” Journal of IET Circuits Devices and Systems, vol. 10 (3), pp. 209-219, May 2016.  DOI: 10.1049/iet-cds.2015.0243 (SCIE)
  4. Neeta Pandey, Deva Nand, V. Venkatesh Kumar, Varun Kumar Ahalawat, Chetna Malhotra, “Realization of OFCC based Transimpedance Mode Instrumentation Amplifier” Journal of Advances in Electrical and Electronic Engineering, vol. 14 (2), pp. 162-167, June 2016. DOI 10.15598/aeee.v14i2.1551 (Scopus)
  5. Deva Nand, Neeta Pandey, “A new proposal for OFCC based Instrumentation amplifier” International Journal of Electrical and Computer Engineering (IJECE), vol. 7 (1), pp. 134, December 2016. DOI: http://doi.org/10.11591/ijece.v7i1.pp134-143 (Scopus)
  6. Deva Nand, Neeta Pandey, “Transadmittance Mode First Order LP/HP/AP Filter and its Application as an Oscillator” IOP Conf. Ser.: Mater. Sci. Eng. Vol. 225 (012150), 2017. https://doi.org/10.1088/1757-899X/225/1/012150 (Scopus)
  7. Deva Nand, Neeta Pandey, Rajeshwari Pandey, Prateek Tripathi, and Prashant Gola, “OFCC based voltage and transadmittance mode instrumentation amplifier”, AIP Conference Proceedings, vol. 1859 (020109), 2017.  http://dx.doi.org/10.1063/1.4990262 (Scopus)
  8. Deva Nand, Neeta Pandey, “New Configuration for OFCC based CM SIMO filter and its application as Shadow filter” Arabian Journal for Science and Engineering (Springer), vol. 43, pp. 3011-3022, 2018. https://doi.org/10.1007/s13369-017-3058-1 (SCIE)
  9. Prateek Pahalwan, Prateek Tripathi, Prashant Gola, Neeta Pandey, Deva Nand, “Programmable Gain Amplifier using Operational Floating Current Conveyors” Int. Journal of Electronics and Communications, AEU, (Elsevier), vol. 90, pp. 163-170, 2018. https://doi.org/10.1016/j.aeue.2018.04.022 (SCI)
  10. Kumar, A., Singh, D. & Nand, D. A Novel CFDITA-Based Design of Grounded Capacitance Multiplier and Its Transpose Structure, Circuits Syst Signal Process 41, 5319–5339 (2022). https://doi.org/10.1007/s00034-022-02032-4 (SCIE)
  11. Deva Nand, Neeta Pandey, Varun Bhanoo, Ashmin Gangal, “Operational floating current conveyor based TAM & TIM shadow filter” International Journal of Information Systems & Management Science, Vol. 1, No. 1, pp. 103-115, 2018. (Scopus)
  12. Neetika Yadav, Neeta Pandey, Deva Nand, “Leakage reduction in dual mode logic through gated leakage transistors, Microprocessors and Microsystems, Volume 84, 2021, 104269, https://doi.org/10.1016/j.micpro.2021.104269 (SCI)
  13. MUNINDRA, Nand, D. Nonlinearity and scaling trends of quasiballistic graphene field-effect transistors targeting RF applications. J Comput Electron 20, 2379–2386 (2021). https://doi.org/10.1007/s10825-021-01772-x (SCI)
  14. Munindra, Nand, D. Nonlinearity Analysis of Quantum Capacitance and its Effect on Nano-Graphene Field Effect Transistor Characteristics. J. Electron. Mater. 51, 4616–4624 (2022). https://doi.org/10.1007/s11664-022-09639-y (SCI)
  15. Kumar, A., Singh, D. & Nand, D. A Novel CFDITA-Based Design of Grounded Capacitance Multiplier and Its Transpose Structure. Circuits Syst Signal Process 41, 5319–5339 (2022). https://doi.org/10.1007/s00034-022-02032-4 (SCIE)
  16. Yadav, N., Pandey, N. & Nand, D. LDML: A Proposal to Reduce Leakage Power in DML Circuits. Wireless Pers Commun 129, 1009–1024 (2023). https://doi.org/10.1007/s11277-023-10170-4 (SCI)
  17. Neetika Yadav, Neeta Pandey, Deva Nand, “Modified Dual Mode Transmission Gate Diffusion Input Logic for Improving Energy Efficiency” Journal of Circuits, Systems and Computers, Vol. 32, No. 10, 2350171 (2023). (SCIE)
  18. Kaul, A., Rewari, S. & Nand, D. Hetero-dielectric macaroni channel cylindrical gate all around field effect transistor (HD-MC CGAA FET) for reduced gate leakage analog applications. Microsyst Technol 30, 599–611 (2024). https://doi.org/10.1007/s00542-023-05577-9 (SCI)
  19. Aapurva Kaul, Snehlata Yadav, Sonam Rewari, Deva Nand, “Computational modelling of cylindrical-ferroelectric-dual metal-nanowire field effect transistor (C-FE-DM-NW FET) using landau equation for gate leakage minimization”, Micro and Nanostructures, Volume 191, 2024, 207851, https://doi.org/10.1016/j.micrna.2024.207851. (SCI)
  20. Kumari, Sweta and Nand, Deva, “Realization of nth Order Wave Active Low-Pass Filter Using Differential Difference Current Conveyor”, Journal of Circuits, Systems and Computers, vol. 33, No. 10, pp. 2450180, 2024, doi:10.1142/S0218126624501809. (SCIE)
  21. Kumari, S., Nand, D. & Kant, S. MOS-based electronically tunable current-mode dual-output full-wave rectifier using single DDCCTA. Electr Eng 107, 4203–4213 (2025). https://doi.org/10.1007/s00202-024-02736-7 (SCI)
  22. Aapurva Kaul, Sonam Rewari and Deva Nand, “Double Metal Gate Macaroni Nanowire FET (DMGM-NFET) for Improved Performance and Off-State Leakage Reduction”, 2024 ECS J. Solid State Sci. Technol. 13 103010. doi:10.1149/2162-8777/ad775d (SCI)
  23. Kumari, Sweta and Nand, Deva, "Simplified Wave Active Filter: A Novel Design in Current Mode with Single EX-CCCCTA, Journal of Circuits, Systems and Computers, vol.34, No. 04, pp.2550091,2025, doi:10.1142/S0218126625500914 (SCIE)
  24. A. Kaul, S. Yadav, S. Rewari and D. Nand, "Analytical Modeling of Temperature-Resilient Cylindrical Gate Engineered Ferroelectric Nanowire Field-Effect Transistor," in IEEE Transactions on Dielectrics and Electrical Insulation, vol. 32, no. 5, pp. 2674-2682, Oct. 2025, doi: 10.1109/TDEI.2025.3538754. (SCI/SCIE)
  25. Aapurva Kaul, Sonam Rewari, Deva Nand, “Performance-Oriented Analytical Modelling of Channel Engineered-Macaroni Induced Gate All Around Field Effect Transistor for Off-State Leakage Mitigation” 2025 ECS J. Solid State Sci. Technol. 14 103002, doi:10.1149/2162-8777/ae09d8 (SCI)
  26. Sweta Kumari, Deva Nand, Surya Kant, "Realization of TAM-based PD, PI, PID controllers utilizing DDCCTA for closed-loop system applications, Franklin Open,Vol. 12, 2025, 100380, https://doi.org/10.1016/j.fraope.2025.100380.

BOOKS/BOOK CHAPTERS (IF ANY)

Book Chapter:

1. Design and Performance Exploration of Macaroni Channel-Based Ge/Si Interfaced Nanowire FET for Analog and High-Frequency Applications Using Machine Learning, by Aapurva Kaul, Amit Das, Shivani Yadav, Sonam Rewari, Deva Nand, Machine Learning for Semiconductor Materials, 1st Edition, 2025, CRC Press.

PATENTS (IF ANY)

Patents:

Patents Granted: 02

Patents Published: 01

Patents Applied: 01

HONOURS AND AWARDS (IF ANY)

Honours and Awards:

•Commendable research award for publications in year 2018, 2021, 2022, 2023, 2024.
•Key Note speaker in the 1st International conference on applications of artificial Intelligence in Computational Intelligence and Communication Technologies(ICAAI-2025), held on Nov 13-14, 2025, Organized by Department of CSE , NSUT East campus, Delhi.
•Best Paper Award in MCCS-2023, ICEEICT-2023.
•“Certificate of appreciation” for invaluable contribution as a member for evaluation of the teams in the Internal Hackathon held on 15th September, 2023 organized by Smart India Hackathon 2023 (SIH-2023), DTU, Delhi.

SPONSORED/CONSULTANCY PROJECTS

1. ANRF-Advanced Research Grant: Development of Low Cost Portable Multispectral Camera for Educational Tool and Diagnostic Tool using Raspberry Pi, Rs. 85,35,840/-, Date : 09-Jun-2026, Dr. Deva Nand (PI), Dr. S. Majumdar (Co-PI), File Number : ANRF/ARG/2026/003863 (Accepted for Technical Evaluation)

2. FIRP Project Proposal-1:  Design And Development of an Adaptive Hybrid Energy Management System With Ai-based Predictive Battery Failure and Intelligent Battery Swapping For Electric Rickshaws, Rs. 10,00,000/-, Date: 15.04.2026, Dr. Deva Nand (PI), Dr. Garima (Co-PI), PRAYAS Portal ID: 79, PRID: 1436 (Applied)

3. FIRP Project Proposal-2: Development of a Grid-Connected Utility-Scale Solar Power Plant with Integrated Energy Storage System (ESS), Rs. 10,00,000/-, Date: 24.04.2026, Dr. Garima (PI), Dr. Deva Nand (Co-PI), PRAYAS Portal ID: 89, PRID: 1456 (Applied)

START-UPS (IF ANY)

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MOOC COURSES DEVELOPED (IF ANY)

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PROFESSIONAL DEVELOPMENT

FDPs/Seminars/Workshops:

  1. Organized One Day Workshop on “Atomistic Modeling using Synopsis Quantum ATK for Nanomaterials/Nano Devices” on 11th January, 2024 as a Convenor of Vinod Dham Centre of Excellance for Semicondcutors and Microelectronics. 
  2. Organized One Week workshop for UG students as Coordinator on “Digital System Design using EDA Tools” during 10th -14th June, 2024.
  3. Organized One week FDP on “Advancement and Challenges in VLSI Design and Nanoscale Devices” during 27th – 31st May, 2024 in Deptt of ECE, DTU.
  4. Organized an Expert Lecture/talk of Prof. P.K. Basu, Institute of Radio Physics and Electronics at the University of Calcutta on 24.05.2023 for UG/PG/Ph.D students.
  5. Organized an Expert lecture on “Clocking a Semiconductor chip: Timing Perspective” by Mr. Babul Anunay Principal Engineer, NXP Semiconductors, Noida on 21 March 2024.
  6. Organized Online Technical Seminar/Webinar on “Break Into VLSI Design: From Classroom Concepts to Industry-Ready Skills” by Mr. Anuj Panwar Senior ASIC/RTL Design Engineer - NVIDIA, Santa Clara, December 14, 2025.
  7. Organized an Expert Lecture/Technical Seminar (NXP Campus Connect Program) by Ms. Divya, Senior System & Application Engineer, NXP Semiconductors, India on August 19, 2025.

ADVISEES

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ANY OTHER INFORMATION

Will be updated soon...