Dr. CHAUDHRY INDRA KUMAR

• Assistant Professor, Department of Electrical Engineering, Delhi Technological University, Delhi, India (Jan. 2020 – Present)

• Assistant Professor in Dept. of Electrical and Electronics Engineering, BITS Pilani, Goa Campus, Goa, India (Dec. 2019 to Jan 2020)

• Research Associate in Dept. of Electronics and Communication Engineering, IIT, Roorkee, Uttarakhand, India (Jul. 2019 to Oct. 2019)

• Assistant Professor in Dept. of Electronics and Communication Engineering, College of Engineering Roorkee (COER), Roorkee, Uttarakhand, India from (Aug. 2011 to Jun. 2014)

A. Theory

• Analog and Digital Electronics (M.Tech.)

• Analog Filter Design (M.Tech.)

• Digital VLSI Design (B. Tech.)

• Digital Circuit And System (B.Tech.)

• Digital System Design (B.Tech.)

• Electronic Devices and Circuit (B.Tech.)

• Antenna and Wave Propagation (B. Tech.)

• Linear integrated Circuits (B.Tech.)

• Analog Electronics (B. Tech.)

• Digital Signal processing (B.Tech.)

• roller Laboratory (B.Tech.)

• Digital Signal Processing Laboratory (B.Tech.)

• Basic Electrical Engineering Laboratory (B. Tech)

• Electromagnetic Filed Theory (B.Tech.)

B. Laboratory 

• Analog Electronics Laboratory (B.Tech.)

• Electronic Devices and Circuit Laboratory (B.Tech.)

• Linear Integrated Circuits Laboratory (B.Tech.)

• Microprocessor and Microcont

IEEE

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• N Kumar, Chaudhry Indra Kumar and N Pandey, "High-performanceand robusttriple nodeupsetradiationhardenedlatch design" AEU -InternationalJournal ofElectronics and Communications, 2025.

• N Kumar, Chaudhry Indra Kumar and N Pandey “High-performance radiation hardened latch using Schmitt trigger” in Elsevier Integration, the VLSI Journal, 2025

• Chaudhry Indra Kumar, L Gautam, and N Pandey “Variation aware resilient flip-flop design for low-voltage applications” in International Journal of Electronics, 2025

• Chaudhry Indra Kumar, A Chaudhary, and S Upadhyaya “Design of high performance energy efficient CMOS voltage level shifter for mixed signal circuits applications” in Elsevier Integration, the VLSI Journal, 2024

• R. Shekhar, and Chaudhry Indra Kumar, “Design of Highly Reliable Radiation Hardened 10T SRAM cell for Low Voltage Applications” in Elsevier Integration, the VLSI Journal, 2022

• D. Kushwa, Chaudhry Indra Kumar, N. Gupta, A. Joshi, S. Miryala, R. Joshi, S. Dasgupta, and B. Anand, “A Robust Energy-Efficient 10T-Based Compute In-Memory XNOR and Accumulation Approach for Binary Neural Networks” in IEEE TCAS-II, 2022

• Chaudhry Indra Kumar, "A Highly Reliable Energy Efficient Double Node Upset Tolerant Latch", in Journal of Circuits, Systems and Computers, 2021.

• Chaudhry Indra Kumar, and Bulusu Anand, "A Highly Reliable and Energy Efficient Radiation Hardened 12T SRAM Cell Design", in IEEE Transactions on Device and Material reliability, 2020.

• Chaudhry Indra Kumar, and Bulusu Anand, "A Highly Reliable and Energy Efficient Triple-Node-Upset Tolerant Latch Design", in IEEE Transactions on Nuclear Science, 2019.

• Chaudhry Indra Kumar, I. Bhatia, A. K. Sharma, D. Shegal, H. S. Jatana, and Bulusu Anand, " A Physics based Variability Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage Latches", in IEEE Transactions on Very large Scale Integration, 2019.

• Chaudhry Indra Kumar, A. K. Sharma, Rajendra Pratap and Bulusu Anand, "An energy-efficient variation aware self-correcting latch", in Elsevier Microelectronics Journal, 2019.

• Chaudhry Indra Kumar, and Bulusu Anand, "High Performance Energy Efficient Radiation Hardened Latch for Low Voltage Applications", in Elsevier Integration, the VLSI Journal, 2019.

• Chaudhry Indra Kumar, and Bulusu Anand, "Design of highly reliable energy-efficient SEU tolerant 10T SRAM cell", in IET Electronics Letters, 2018.

P. MANDAL, R. SHARMA, CHAUDHRY INDRA KUMAR "A SYSTEM AND METHOD FOR PROVIDING REALTIME AVAILABILITY OF ELECTRIC CHARGING SLOTS FOR VEHICLES"

• Honored with the Research Excellence Award by Delhi Technological University in the year 2025

• Honored with the Research Excellence Award by Delhi Technological University in the year 2023

• Qualified Graduate Aptitude Test Engineering (National Level Engineering Entrance Examination) in 2009.

• Teaching Assistant Fellowship in Master of Technology from Ministry of Human Resource and Development, Government of India 2009-2011

• Teaching Assistant Fellowship in Ph.D. from Ministry of Human Resource and Development, Government of India