Professional Experience details:

Designed & Tested the ESOM Gigabit Ethernet client port FPGA for the EM6 board.

 

Design and implemented the Hardware design development and unit testing process.

Design and development of Hardware design development & unit testing process to be used within the organization. Also involved in the testing & debugging of the STM-1 CPE card.

Designed the STM-1 line card for NGSDH system.

This card Rx & Tx STM-1 electrical/optical signal and does the complete SOH processing of the STM-1 frame.  On the back-plane side, it generates & receives the telecom bus. The processor interface is through the backplane processor bus. This card consists of an Xilinx FPGA, which performs SOH processing of the STM-1 frame, including pointer generation for STM-1.   

Designed FPGA for pointer generation

This FPGA does the AU-4 level pointer generation in the ADD direction. The Design is implemented using VHDL. It is mapped into the Xilinx FPGA Spartan-2 XC2S150 with pointer interpretation and SOH processing FPGA block.

Tools Used: Synopsys FPGA Compiler II for synthesis, Synopsys SCIROCCO simulator for front-end& back annotating timing simulation, and Xilinx design manager for backend.

 

Designed and tested STM-1 electrical feeder Card for CSTM-1 systems

This card provides interface for STM-1 electrical on line side and complete SOH processing, Pointer interpretation and VC-4 path level processing. On tributary side it provides the interface for 139.364 Mbps and 2.048 Mbps tributaries. This card has Xilinx FPGA Spartan-2 and for mapping and de-mapping of 2.048 Mbps Intel 2MB Mapper/De-mapper device, for 139.264 Mbps Transwitch L4M device.

Tools Used: VISULA 5.1g from ZUKEN REDAC for PCB layout and GC-CAM used for Gerber file generation. For debugging Controller Circuit AMC-68302 emulator was used.

Designed FPGA for overhead byte processing of STM-1 frame

This FPGA does the RSOH, MSOH pointer byte, VC-4 path level overhead byte processing. It extracts and inserts overhead byte from/in STM-1 frame. It provides CIJI and SPE pulse for various devices of STM-1 electrical feeder card for Mapping and De-mapping E-1 and E-4 PDH signal. This is mapped into XC2S150 spartan-2 Xilinx FPGA. It is designed using VHDL.

Tools Used: Synopsys FC2, Synopsys VSS simulator for front-end and timing simulator, Xilinx designs manager as backend tool.

 

Designed FPGA for DTMF detection using digital filters

The FPGA was used to detect which key is pressed in a DTMF telephone handset. The telephone keypad has 16 keys and each key is recognized by two frequencies, one is low frequency group (600-900 Hz) and other is high frequency group (1200-1700 Hz). For this Xilinx FPGA series 4000 was used. Design was implemented using VHDL.

Tools Used: Synopsys VSS simulator, Synopsys FC2, Xilinx design manager.

 

Designed the Tributary Unit Payload Processor (TUPP) FPGA for STM-1 system.

Designed the Tributary Unit Payload Processor FPGA for STM-1 using VHDL, which performs the TU pointer processing using time sliced pointer interpreter and pointer generator state machine of the various tributaries within the STM-1 frame.  A valid combination of TU-12 & TU-3 can be processed by this FPGA.

By processing TU pointer it aligns the tributary units by passing the AU justifications to TU justifications and also perform multi-frame alignment, which is required for performing switching of the tributaries among different STM-1 lines.

It also eases the work of the mappers in the downstream. It also performs the TU path overhead processing and alarm monitoring of the various tributaries inside the STM-1 frame.

Tools Used: Synopsys VSS simulator, Synopsys FC2, Xilinx design manager.

 

Studied & Tested the VHDL code of the K1K2 processing FPGA for STM-1 system

Studied the VHDL code of the K1K2 processing fpga, which is designed for initiating protection switching, automatic protection switching (APS) in the ring for STM-1 system. Tested this FPGA on the test bench. This fpga sits on east & west line cards and a state m/c runs on each card. These 2 fpga communicate through the back plane interfaces of the system.

 

Designed and tested P34 card

This P34 card maps three independent 34 MBPS PDH tributary into STM-1 frame via

TU-3 to VC-4 multiplexing structure in TX. Direction. It extracts three 34mbps tributaries from the Rx. STM-1 frame.

This card also has processor circulatory, which provide processor interface to various devices. This card has ALTERA MAX PLD consists of 68302 processor i/f, counter for generating 64khz clock and other glue logic.

Tools Used: VISULA  from ZUKEN READAC for PCB layout and GC-CAM used for Gerber generation. For debugging Controller circuit AMC-68302 emulator was used.

 

System Integration and testing of the STM-1 system

System integration involves the testing of the whole system with various cards in the system. It involves testing of the cards in the system, cards data path and control interface through back-plane by configuring the various card through Rs232 interface. It also involves the debugging of the various interfaces between card-card, card-back plane.

• Attended 4 days Intensive training programme on VHDL Synthesis   by CMR Automation

PVT.  LTD. New Delhi

• Attended 13th International conference on VLSI design, held at Calcutta.
• Attended 16th International conference on VLSI design, held at New Delhi.
• Attended various seminars/workshops organized by Altera, Xilinx, Synopsys etc.