• Ph.D. (Electronics) -  DEC 2005-FEB 2009                             

Thesis Title: Analytical Modeling and Simulation of Gate Electrode Workfunction and Dielectric Engineered Recessed Channel MOSFET in Sub-100nm Regime, Semiconductor Devices Research Laboratory, Department of Electronic Science, South Campus, Delhi University.

• M.Sc in Electronics - South Campus,  Delhi University(GOLD MEDALIST)- 85%  UNIVERSITY TOPPER - JULY 2003-JULY 2005.        
• B.Sc(H) in Electronics,Acharya Narendra  Dev College, Delhi University- 82%   COLLEGE TOPPER - JULY 2000-MAY 2003.                                         

TECHNICAL EXPERIENCE :

1. Summer Internship in FPGA Design of DS-BPSK Modulator-     May2004-July2004    

     Defence Electronics Applications Laboratory (D.E.A.L), DRDO, Ministry Of Defence, Dehradun

2. Worked as a Design Engineer in Saora Informatics India  Pvt Ltd.,  Nehru Place, New Delhi – 18th July 2005-21 Oct 2005 

  Worked on the design of RSS Reader, Patent Filing etc.

3. Had been to the Saora’s Japan (Headquarters) Office for a month (24^th July 2005-21^st August 2005) for project submission.

4. Taught M.Sc.Electronics (July’06-May’10) at Department of Electronic Science, University of Delhi, South Campus, New Delhi as a Visiting Faculty.

 Subjects Taught: Advanced Analog Design, PSPICE, MULTISIM and VHDL Lab, Network Synthesis

5. Taught B.Sc.(H) Electronics (August’08-April’09) at Acharya Narendra Dev College, Department of Electronics, University of Delhi, South Campus, New Delhi as an ADHOC Lecturer.

   Subjects Taught: IC Technology, Numerical Analysis and FORTRAN, Electronic Circuits Lab.

6. Taught B.Sc.(H) Electronics (July’09-April’10) at Deen Dayal Upadhyaya College, Department of Electronics, University of Delhi, South Campus, New Delhi as an ADHOC Lecturer.

    Subjects Taught: Digital Electronics, Power Electronics, Mathematical Physics, Electronics Circuits Lab.

7.  Involved with M.Tech (Material Science and Tech.), B.Tech-(Engg. Phy.) in Department of Applied Physics, Delhi Technological University (Formerly Delhi College of Engineering), Delhi as Professor.

   Subjects Taught: Digital Electronics, Microprocessors and Interfacing, Engineering Materials, VLSI  and FPGA Design, Digital Electronics Lab, Microprocessors and Interfacing Lab, Communication Systems Lab, Mobile and Satellite Communication Lab, VLSI and FPGA Design Lab.

HONOURS/AWARDS/DISTINCTIONS:

• Fellow, National Academy of Sciences, India (NASI) (Youngest Awardee in 2024)
• YEARLY CITATION AWARD-EARLY RESEARCH IMPACT AND INFLUENCE AWARD for excellence in research, Delhi Technological University, 2024.

• Commendable Research Award for excellence in research, Delhi Technological University, 2024.

• PREMIER Research Award for excellence in research, Delhi Technological University, 2024.

• Received best paper award (Ph.D. Scholar-Shaveta) in 2^nd International  Conference on Emerging Trends in Information Technology and Engineering (ICETITE-2024) at VIT Vellore, Feb 22-23, 2024
• Received best paper award (Ph.D. Scholar-ANSHUL) in 11^th International  Conference on Microelectronics, Circuits and Systems (Micro-2024) at Delhi Technological University, Delhi, May 16-17, 2024
• Received best paper award (Ph.D. Scholar-RASHI MANN)  in 10^th International  Conference on Microelectronics, Circuits and Systems (Micro-2023) at Guwahati, Assam, July 01-03, 202
• CUMULATIVE CITATION AWARD:SILVER for excellence in research, Delhi Technological University, 2023
• YEARLY CITATION AWARD-EARLY RESEARCH IMPACT AND INFLUENCE AWARD for excellence in research, Delhi Technological University, 2023
• Commendable research award for excellence in research, Delhi Technological University, 2023.
• Received best paper award (Ph.D. Scholar-bhavya kumar)  in 8^th International  Conference on Signal  Processing and Communication (ICSC-2022) at JIIT, NOIDA, UP, Dec 01-03, 2022
• SERB-POWER Fellowship, SERB-DST, Govt. of India
• Commendable Research Award for excellence in research, Delhi Technological University, 2022.
• Selected in Stanford University List of Top 2% Scientists Worldwide, 2021 and 2022.
• Name appeared in IEEE transactions on electron devices list of golden reviewers-2021
• Commendable research award for excellence in research, Delhi Technological University, 2021
• RECOGNITION FOR EXCELLENCE IN TEACHING AWARD AT UNIVERSITY LEVEL, Delhi Technological University, 2020

• Commendable research award for excellence in research, Delhi Technological University, 2020

• Commendable research award for excellence in research, Delhi Technological University, 2019
• Premier Research award for excellence in research , Delhi Technological University, 2018
• commendable research award for excellence in research , Delhi Technological University, 2018
• YOUNG WOMEN IN SCIENCE (Specialization -Electronics), Venus International Women Awards (VIWA-2017)
• Recipient, Bharat Vikas Award, Institute of Self Reliance, Bhubaneshwar, India, 2016
• Ambassador, Asian Council of Science Editors-2016
• Young Scientist Award for contribution in the field of Microelectronics, Venus International Foundation, Center for Advanced Research and Design (VIFRA-2015), 2015.
• 2nd academic brilliance award- 2014: Certificate of excellence by education expo, Research   wing for excellence in professional education and industry.
•  Pearson Teaching Award for Innovation in Teaching at Undergraduate Level, 2013.
•  DST Fast Track Young Scientist Award-2012, Ministry of Science and Technology, DST.
• “ROBERT BOSCH AWARD”- 4^th Grade in Electronic Displays Conference, Nuremberg, Germany, February 2012.
• “BEST PAPER AWARD” in International Conference on Electronic Design and Automation, Bangkok, December 2011
• Publications : 213  Papers in Various Refereed International and National Journals and Conferences.
•  FULL FELLOWSHIP in International Workshop on Physics of Semiconductor Devices  (IWPSD-2007), Mumbai, 2007
• “BEST STUDENT PAPER AWARD” in National Conference on Trends in VLSI and Embedded System, Indian Microelectronics Society, (IMS-2007), Chandigarh, India.
• DU FELLOWSHIPS  : Scholarship scheme for academic (2003-2005) excellence at the graduation and post graduation level.
• M.Sc. ELECTRONICS (GOLD MEDALIST), Delhi University (2003-2005)
•  SHANTI DEVI BHARGAVA MEMORIAL MEDAL (2006) for excellence in academics in M.Sc. Electronics (2003-2005).    
• TALENT APPRECIATION AWARD (2006) for academic excellence in M.Sc. Electronics (2003-2005)
• Got 5^th position in B.Sc(H)Electronics, Delhi University.
• Awarded cash prize and Certificate of Merit for securing 1^st position in Delhi University, South Campus and the college in B.Sc(H)Electronics Part-I ; and 1^st position in the college in B.Sc(H)Electronics Part-II and Part-III.
• UGC–NET-JRF (2004) QUALIFIED(Lectureship & Fellowship)
• Worked as UGC–SRF (from December 2007 to July 2008)

• Reviewer, Energy Conversion and Management, Elsevier
• Reviewer, International Journal of Modeling and Simulation, Taylor and Francis
• Reviewer, Superlattices and Microstructures, Elsevier
• Reviewer, Defense Science Journal, DRDO
• Reviewer, Microsystem Technologies Journal, Elsevier
• Reviewer, Progress in Electromagnetic Research Journal, USA
• Reviewer, Oxford University Press for Few chapters of book on Engineering Physics
• Name appeared in Who’s Who in America and Who’s Who in the World, USA in 2010.
• Reviewer of IEEE Transactions on Nanotechnology
• Reviewer of Journal Of Energy and Power Engineering, David Publishing Company, NY, US
• Reviewer of IEEE Transactions on Electron Devices
• Reviewer of IEEE TENCON Conference
• Reviewer of Microelectronics Journal, Elsevier.
• Reviewer of Journal Of Electronics and Electrical Engineering Research.
• Reviewer of Physica-E: Low-Dimensional Systems and Nanostructures.
• Reviewer of IETE Technical Review.
• Reviewer of International Journal of Physical Sciences (IJPS).
• Reviewer of International Journal of Numerical Modeling: Electronic Networks, Devices and Fields, IOP.
• Reviewer of International Conference - Asia Pacific Microwave Conference (APMC)-2008 held from 16-19, December 2008 in Hong Kong Convention and Exhibition Center, Hong Kong, China

         ONGOING SPONSORED/RESEARCH PROJECTS:

   #  Received IEEE Grant for the Project applying industry standards titled “Design, Development and Integration of Industry Standard Compliant Solutions for a Smart Grid”-2011. (Faculty Advisor) Project Cost: USD 800.

  #   Received a project grant of Rs.2 Lacs for the Design and Fabrication of Autonomous Surface Vehicle for participation in 5^th Robot International Competition held from June 20-24, 2012 in USA from DTU

  #    Received a project grant of Rs.2.7 Lacs for the Design and Development of Smart Green Vehicle from DTU in 2012. 

  #  DST Fast Track Project for “Characterization, Simulation and Equivalent Circuit Analysis of Silicon Nanowire Transistors For High Performance Applications in Wireless and RF Technology”- SERC,  Department of Science & Technology, Govt. of India, 2013-2017. (Project Investigator) Project Cost-Rs. 18.6 Lacs

#     DTU Sponsored Research Project Grant for “TCAD Analysis and Simulation of Gate Material Engineered Junctionless FinFET For High Performance Analog and Wireless Application.” Project Cost: Rs.4.05 Lacs (2019-2021)

#       SERB Power Fellowship and Research Grant of Rs.38, 10, 000/- (Rupees Thirty Eight Lakhs Ten Thousand Only), 2022.

SPECIAL ACHIEVEMENTS/BOOKS/MONOGRAPHS/CHAPTERS:

• Editor, Microelectronics, Circuits and Systems-Lecture Notes in Electrical Engineering, Springer, 2023

• Contributed a Chapter titled “Numerical study of symmetric underlap S/D high-ĸ spacer on JAM-GAA FinFET for low-power applications”, Emerging Low-Power Semiconductor Devices Applications for Future Technology Nodes,  Publisher: CRC Press, Routledge Taylor and Francis Group, 2022. (Bhavya Kumar and Rishu Chaujar)

• Contributed a chapter titled "High Switching Performance of Novel Heterogeneous Gate Dielectric—Hetero-Material Based Junctionless-TFET." Microelectronics, Circuits and Systems. Springer, Singapore, 2021. 3-12.( Sharma, Samriti, and Rishu Chaujar.)

• Contributed a chapter titled " Fin Aspect Ratio Optimization of Novel Junctionless Gate Stack Gate All Around (GS-GAA) FinFET for Analog/RF Applications" Microelectronics, Circuits and Systems. Springer, Singapore, 2021. (Bhavya Kumar and Rishu Chaujar.)
• Contributed a Chapter titled “Static and CV Analysis of Gate Engineered GAA Silicon Nanowire MOSFET for High-Performance Applications”, pp.59-68 in a book titled “Energy Systems, Drives and Automations” by Afzal Sikander · Dulal Acharjee ·Chandan Kumar Chanda ·Pranab Kumar Mondal ·Piyush Verma, published by Springer, 2020 (Neha Gupta, Ajay Kumar, and Rishu Chaujar)
• Contributed a Chapter titled “Built-in Reliability Investigation of Gate-Drain Underlapped PNIN-GAA-TFET for Improved Linearity and Reduced Intermodulation Distortion”, pp.205-213 in a book titled “Energy Systems, Drives and Automations” by Afzal Sikander · Dulal Acharjee ·Chandan Kumar Chanda ·Pranab Kumar Mondal · Piyush Verma, published by Springer, 2020 (Rahul Pandey, Jaya Madan, Rajnish Sharma, Minaxi Dassi, and Rishu Chaujar)
• Contributed a Chapter titled “Detection of Hazardous Analyte Using Transparent Gate Thin-Film Transistor”, pp.197-204 in a book titled “Microelectronics and Telecommunication Engineering” by Devendra Kumar Sharma, Valentina Emilia Balas, Le Hoang Son, Rohit Sharma, Korhan Cengiz  published by Springer, 2020 (Ajay Kumar, Amit Kumar Goyal, Manan Roy, Neha Gupta, MM Tripathi, Rishu Chaujar)

• Invited Presentation on “Transparent Gate Recessed Channel MOSFET: A Protein Biomarker for Early Stage Diagnostics” in Nanoelectronics and Miniaturization session in 9th IndoGerman Frontiers of Engineering (INDOGFOE) Symposium 2017 held in Jaipur from March 9-12, 2017.
• Contributed a Chapter titled “Effect of Nanocsale Structure on Reliability of Nano Devices, Sensors and MEMS”, pp.239-270 in a Book titled “Outlook and Challenges of Nano Devices, Sensors and MEMS” by Ting Li and Ziv Liu published by Springer, 2017.
• Editorial Board Member, Mantech Publications Journals, 2016
• Editorial Board Member, Journal of VLSI Design Tools and Technology, 2015
• Editorial Board Member, Journal of Renewable energy and Resources, 2015
• Editorial Board Member, Journal of Nano Technology and Its Application in Engineering and medicine, 2015
• Editorial Board Member, International Journal for Innovative Research in Science and Technology, 2015.
• Editorial Board Member, International Journal for Scientific Research and Development, 2015.
• Advisory Board Editorial Member, Journal of Electronic and Electrical Engineering(2013-Till Date)
• Editor, Journal of Embedded Systems, Science and Education Publishing, USA (2013-Till Date)

ASSOCIATION WITH PROFESSIONAL SOCIETIES:

• Fellow-National Academy of Sciences, India (NASI) (2024)-Youngest Awardee in 2024
• Fellow- Institution of Electronics & Telecommunication Engineers (IETE), India (2018)
• Fellow-Optical Society of India (2023)
• Professional Member-Association of Computing Machinery (ACM) (2024)
• Member-American Physical Society(APS) (2024)
• Member-American Chemical Society (ACS) (2024)
• Member-IEEE Women in Engineering(2024)
• Senior Member-IEEE Electronics Packaging Society (2024)
• Senior Member – IEEE Professional Organization, USA (2016-Till Date)
• Life Member, National Academy of Sciences (NASI), India(2016)
• Life Member-Indian Society for Technical Education (ISTE), India
• Life Member- Indian Women Scientists’ Association, India.
• Life Member- Indian Science Congress Association, India.
• Life Member- Semiconductor Society of India, India.
• Life Member-Materials Research Society of India.
• Member – IEEE Communication Society, USA (2008-Till Date)
• Member - International Association of Engineers, Hong Kong (2008-Till Date)
• Member-American Nano Society, USA (2011-Till Date)
• Member-Green ICT Community, IEEE (2014-Till Date)
• Member- IEEE Council on RFID (2014-Till Date)
• Executive Member- IEEE Electron Devices Society (2015-till date)
• Member-International Association of Advanced Materials (2016-till date)

M.Tech.Thesis Guidance: 15 students guided in past years

Ph.D. Research Guidance

1. “TCAD Analysis and Simulation of Gate Electrode Workfunction Engineered (GEWE) Silicon Nanowire MOSFET for high performance Analog and RF Applications” - Neha Gupta- June 2017
2. “Simulation and Analysis of Gate All Around Tunnel FET for High Performance Analog and RF Applications” - Jaya Madan, March 2018.
3. “Design and Simulation of SiC based Rear Contact Si and SiGe Solar Cell for Standalone and Tandem Applications” – Rahul Pandey, April, 2018
4. “Microwave Based Ferromagnetic Resonance in Magnetic Thin Films induced by Spin Hall Effect” - Saood Ahmad, August 2018
5. “Study of Superconducting Nanowire towards its application as a Single Photon Detector”- Manju Singh, December 2018
6. “Analytical Modeling and TCAD Simulation of In2O5Sn Transparent Gate Electrode Recessed Channel MOSFET for High Performance Applications”-Ajay Kumar, May 2019.
7. Hemispheric asymmetry analyses through computational neuroscience models with emphasis on EEG microstates: EEG-fMRI data integration approach- Ardaman Kaur, December, 2020

8. Simulation and Analysis of III-V Compound Semiconducting Hetero-Material Based Junction-Less Tunnel FET for Improved Performance- Samriti Sharma, August 2022.

9. TCAD Analysis and Modelling of Gate Stack Gate-All- Around Junctionless Nanowire Field-Effect Transistor for Sensing Applications- Mekonnen Getnet, September 2023.

10. TCAD Analysis and Simulation of T-Gate E-Mode GaN HEMT- Megha Sharma, October 2023.

11. DESIGN AND OPTIMIZATION OF JUNCTIONLESS-ACCUMULATION-MODE GATE-STACK GATE-ALL-AROUND FINFET FOR RF AND BIOSENSOR APPLICATIONS- Bhavya Kumar, November 2023
12. Studies on Technology Computer Aided Design of Double Metal Negative Capacitance FET using DFT and Machine Learning Approach for Analog/Sensing Applications-Yash Pathak, September 2024
13. SELF-CONSISTENT LCAO-BASED DFT ANALYSIS OF FERROELECTRIC AND GATE MATERIAL ENGINEERED NEGATIVE CAPACITANCE FET FOR IMPROVED DEVICE- CIRCUIT PERFORMANCE- Rashi Mann- October 2024.

INTERNATIONAL ACADEMIC CONTRIBUTIONS:

(In Year: 2024)

1. Eminent Speaker, National Seminar on Innovations in the field of Semiconductor and Quantum Physics, organized by Department of Applied Sciences, BHAGWAN PARSHURAM INSTITUTE OF TECHNOLOGY, GGSIPU, Delhi, March 06, 2024.
2. General Chair, 11^th International Conference on Microelectronics, Circuits and Systems (Micro-2024), organized by Vinod Dham Centre of Excellence for Semiconductors and Microelectronics, Delhi Technological University in association with Applied Computer Technology, Kolkatta, May 16-17, 2024.
3. Attended 19th IEEE International Conference on Nano/Micro Engineered and Molecular Systems (IEEE-NEMS 2024), Kyoto held at Kyoto University of Advanced Science (KUAS), Kyoto, Japan from May 2 to May 5, 2024 and presented 2 papers titled “Impact of LCAO-DFT Analysed SI-HFO2 on GS-NCFET for Digital Application” and “DFT Based Analysis of Boron and Nitrogen Passivation at the edge of Armchair Graphene Nanoribbon for Low Power Applications”.
4. Presented Two papers titled “Impact of device parametrics on a 10nm SOI n-FinFET” and “A Novel Dielectric modulated Double Gate Charge-Trapping MOSFET: Ferroelectric Gate Stack and Gaussian Doped Substrate Integration for Enhanced Performance”  in IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS-2024) during 28th to 29th June 2024 at Vemana Institute of Technology, Bengaluru.

(In Year : 2023)

1. Co-Chair, 10th IEEE International Conference on Microelectronics, Circuits and Systems, Guwahati, Assam from July 01-03, 2023.
2. Technical Programme Committee Member, 5th IEEE Sponsored International Conference on Devices for Integrated Circuits (DevIC), Kalyani Government Engineering College, Kolkatta from April 07-08, 2023.
3. Advisory Committee Member, 2nd edition of IEEE Delhi Section International Conference, DELCON-2023, February 24-26, 2023.

(In Year : 2022)

1. Session Chair, International Women’s Day, organized by Dept. of Software Engg and IRD Delhi Technological University, March 08, 2022.

2. Organizing Committee Member, International Women’s Day, organized by Dept. of Software Engg and IRD, Delhi Technological University, March 08, 2022.

3. Invited Talk in WECON-2022: World Engineering Conference on Contemporary Technologies,  May 20- May 21, 2022, Chitkara University, Chandigarh.

4. Session Chair, WECON-2022: World Engineering Conference on Contemporary Technologies, May 20- May 21, 2022, Chitkara University, Chandigarh.

5. Co-Chair, 9th IEEE International Conference on Microelectronics, Circuits and Systems, Jaipur, Rajasthan from June 25-26, 2022.

(In Year : 2021)

1. Co-Chair, 8th IEEE International Conference on Microelectronics, Circuits and Systems, Delhi Technological University, New Delhi from May 08-09, 2021.

2. Session Chair, 4th IEEE Sponsored International Conference on Devices for Integrated Circuits (DevIC), Kalyani Government Engineering College, Kolkatta from May 19-20, 2021.

3. Technical Programme Committee Member, 4th IEEE Sponsored International Conference on Devices for Integrated Circuits (DevIC), Kalyani Government Engineering College, Kolkatta from May 19-20, 2021.

4. Participated in International Summit on Quality Indices in Higher Education-2020, November 06-07, 2020, DTU, Delhi

(In Year: 2020)

1. Co-Chair, 7^th IEEE International Conference on Microelectronics, Circuits and Systems, Delhi Technological University, New Delhi from July 25-26, 2020.
2. Session Chair, 7^th IEEE International Conference on Microelectronics, Circuits and Systems, Delhi Technological University, New Delhi from July 25-26, 2020.
3. Session Chair, 2^nd International Conference on VLSI, Device, Circuit and Systems held in Meghnad Saha Institute of Technology, Kolkatta during July 18-19, 2020.
4. Attended 2^nd International Conference on Inventive Research in Computing Applications (ICIRCA-2020) held in Coimbatore, India on July 15-17, 2020 and presented 2 papers titled “Impact of Metal Strip on Nanoscale Double Gate Overlap Tunnel FET” and “Prediction and forecast for COVID-19 outbreak in India based on Enhanced Epidemiological Models”.
5. Attended and Completed “From the Big Bang to Dark Energy”: an online 4 week non-credit course authorized by The University of Tokyo and offered through Coursera. Completed on June 18, 2020.
6. Participated with a report on “Thermal Reliability of GaN-BTG-MOSFET for High-Performance Applications in Integrated Circuits”, 2020 IEEE 40th International Conference on Electronics and Nanotechnology (ELNANO), Kyiv, Ukraine, 2020.
7. Organizing Committee Member, International Summit on Quality Indices in Higher Education, Delhi Technological University, Delhi.
8. Technical Conference Committee Member, International Summit on Quality Indices in Higher Education, Delhi Technological University, Delhi.

(In Year: 2019)

1. National Advisory Committee Member, 3^rd IEEE Sponsored International Conference on Devices for Integrated Circuits (DevIC), Kalyani Government Engineering College, Kolkatta from March 23-24, 2019.
2. Joint Secretary, International Conference on Atomic, Molecular, Optical and Nano Physics with Applications (CAMNP-2019) held at Delhi Technological University, New Delhi, December 18-20, 2019.

(In Year: 2018)

1. Committee Member, 6^th Edition of International Conference on Wireless Networks and Embedded Systems (WECON), Chitkara University, Punjab from November 16-17, 2018.

1. Invited Lecture in 2^nd European Conference on Electrical Engineering and Computer Science (EECS-2018) held in Bern, Switzerland on December 20-22 on the title “Effect of temperature on GaAs Junctionless FinFET using High-K Dielectric”.

(In Year: 2017)

1. Member- Advisory Board: International Conference on Nanomaterials and Nanotechnology (ICNANO-2017), March 01-03, 2017 at Allahabad, India

(In Year: 2016)

1. Member- Organizing Committee: India International Conference on Information Processing (IICIP-2016), August 12-14, 2016 at Delhi Technological University, New Delhi, India

(In Year: 2015)

1. Attended Tech Connect Innovation World Conference and Expo held in Washington, USA from June 14-June 17 2015 and presented 6 papers.

(In Year: 2014)

        1. Attended Synopsys University Symposium 2014 on Custom IC Design & Device Modelling Tools and Technologies, Hotel Lalit, New Delhi, March 7, 2014.

      2. Attended Seminar on Social Infrastructure-Toshiba’s Vision and Future Plan for India, held on February 14, 2014 at Taj Palace Hotel, New Delhi.

(In Year: 2013)

      1. Attended a TF-DTU-NTU Training Programme on Water Sector Training and Capacity Building Programme for the National Capital Territory of Delhi, India jointly organized by DTU and Nanyang Technological University, Singapore, August 12-17, 2013.

(In Year: 2012)

1. Attended Electronic Displays Conference held in Nuremberg, Germany on Feb 29-March 1 2012 and presented a paper titled “Novel Interactive Propeller Displays”.
2. Attended Embedded World Exhibition & Conference, held in Nuremberg, Germany from Feb 28-March 3 2012.
3. Attended a two-day Mini Colloquia organized by IEEE EDS Delhi Chapter held on March 14-15, 2012 at S.P.Jain Centre Auditorium, University of Delhi, South Campus, New Delhi-110021.

 (In Year: 2011)

1. Attended an International state of the art workshop on Computation Methods for Experimental Spectroscopy (CASTEP-2011), January 5-7, 2011 at Rukmini Devi Institute of Advanced Studies, New Delhi, India.
2. Attended a three day International Conference on “Open Paradigms in Education (OPEN-2011), January 31-February 2, 2011 at India International Center, New Delhi, India
3. Attended a One-Day Workshop on Essentials of PlanAhead sponsored by IEEE held on December 10, 2011 at Indian Institute of Technology, New Delhi.
4. Attended a Three-Day Workshop on Embedded Systems Design using RISC Processor MSP-430 organized by Department of Electronics and Communication Engineering, Delhi Technological University, in collaboration with Texas Instruments, USA held on December 12-14, 2011 at Administrative Building, Delhi Technological University, Delhi.

(In Year: 2009)

1. Member- Organizing Committee: International Symposium on Microwave and Optical Technology (ISMOT)-2009 , December 16-19,2009 in Hotel Ashok, New Delhi, India
2. Member- Organizing Committee: The 18^th WIMNACT(Workshop and IEEE EDS Mini-colloquium on NAnometer CMOS Technology)-New Delhi, India - Mini-Colloquia on "Compact Modeling and Fabrication techniques of advance MOSFET/ HEMT structures", June 04-05, 2009 at University of Delhi South Campus, New Delhi, India sponsored by the IEEE Electron Device Society under its Distinguished Lecturer Program

(In Year: 2008)

1. Attended Asia Pacific Microwave Conference (APMC)-2008, December 16-19, 2008 in Hong Kong Convention and Exhibition Center, Hong Kong, China, and presented papers titled “GEWE-RC MOSFET: High Performance RF Solution to CMOS Technology” and “Gate Material Engineered-Trapezoidal Recessed Channel MOSFET (GME-TRC) for Ultra Large Scale Integration (ULSI)”
2. Attended the URSI Conference “International Union of Radio Science” held on 7^th -16^th August, 2008 at Hyatt Regency, Chicago, Illinois, USA and presented papers entitled “Impact of Multi-Layered Gate Design on Hot Carrier Reliability of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET” and “Investigating the Linearity Performance of DMG AlGaN/GaN HEMT for Improved RF Applications”.
3. Attended Mini-Colloquia on "Compact Modeling of advance MOSFET structures and mixed mode applications" on January 5-6, 2008 at University of Delhi South Campus, New Delhi, India sponsored by the IEEE Electron Device Society under its Distinguished Lecturer Program

(In Year: 2007)

1. Attended the ISDRS Conference “International Semiconductor Device Research Symposium” held on 12^th-14^th December, 2007 at University of Maryland, USA and presented a paper entitled “On-State and Switching Performance Investigation of Sub-50nm L-DUMGAC MOSFET Design for High-Speed Logic Applications”.

NATIONAL ACADEMIC CONTRIBUTIONS:

(In Year: 2024)

1. Chairperson, One Day Workshop on Atomistic Modeling using Synopsys Quantum ATK for Nanomaterials/Nano Devices organized by Vinod Dham Centre of Excellence for Semiconductors and Microelectronics held on January 11, 2024 in Pragyan Hall, DTU.
2. Chairperson, An Academic Interaction with Dr. Satya Gupta, President VLSI Society Of India on the Theme: Semiconductors organized by Vinod Dham Centre of Excellence for Semiconductors and Microelectronics held on January 18, 2024 in Conference Hall, Science Block, DTU.
3. Chairperson, An Industrial Interaction with Mr. MG Hwang-VP and GM, Silvaco, Asia and Mr. Zhao Qingda, MD, Silvaco, Singapore organized by Vinod Dham Centre of Excellence for Semiconductors and Microelectronics held on January 23, 2024 in Conference Hall, Science Block, DTU.

(In Year: 2023)

1. Organizing Committee Member, One Day National Seminar on Recent Advancements in Semiconductor Devices and Materials (RASDM-2023) organized by Dept. of Applied Physics, Delhi Technological University, January 30, 2023.

(In Year: 2022)

1. Session Chair, Intellectual Property Rights (IPRs) and IP Management for Start up, Organized by Dept. of Software Engg and IRD, Delhi Technological University, April 28, 2022.

2. Attended a 3-day Faculty Development Program on NBA Accreditation Procedures organized by IQAC, Delhi Technological University from May 09-11, 2022.

3. Invited Talk in One Week (Online) Faculty Development Program (FDP) on “Recent Development in the Field of Electronics (RDFE-2022)”, Department of Electronic Science, University of Delhi, 25th July to 29th July 2022.

(In Year: 2021)

1. Keynote Speaker, AICTE Sponsored Faculty Development Program on “Sensors fabrication and it’s applications in IoT”, July 02-06, 2021, Graphic Era University, Dehradun, UK.

2. External Expert in DRDO Project “Accelerometer Technology Development”, Ministry of Defence, Govt of India

3. Attended One Week Online Short Term Training Program on INFORMATION SECURITY IN THE ERA OF DEEP LEARNING: Challenges & Opportunities held between 8 February to 12 February, 2021, Department of CSE, Delhi Technological University, Delhi

(In Year: 2020)

1. Attended the National E-Conference On Recent Advancements in Science and Technology (NECRAST 2020) held on 27th-28th July 2020 and presented the research paper titled Static and Thermal Behaviour of Gate Electrode Workfunction Engineered Silicon nanowire MOSFET for temperature tolerance Applications.

2. Distinguished Speaker, One Week Online Faculty Development Program On Technology Computer Aided Design: Simulation for VLSI Devices, Circuits and Systems held on July 20-25, 2020, Jaypee Insitute of Information Technology, Noida, UP.

3. Attended One Week Faculty Development Programme Sponsored by Clariant in collaboration with Frako Germany on Power Quality and Reactive Power Management organized by Department of Electrical Engineering, Delhi Technological University, Delhi from July 06-20, 2020.

4. Attended One Week online Faculty Development Program on “Nascent Methodologies, Challenges and Realms of Research” held from 03 to 07 October, 2020 organized by Department of Electronics and Communication Engineering, Delhi Technological University, Delhi, India.

5. Participated in the TEQIP III sponsored Faculty Development Program (FDP) on “VLSI and Nanotechnology in Energy, Environment, and Neuromorphic Computation in the Centre for Advanced Electronics (CAE) from December 21, 2020 to December 23, 2020 at IIT Indore.

(In Year: 2019)

1. Attended One Week TEQIP-III Sponsored Staff Development Programme on Electronic Design Automation and Documentation Tools organized by Department of Electronics and Communication Engineering, Delhi Technological University, Delhi from July 22-26, 2019.
2. Attended One Week TEQIP-III Sponsored Short Term Training Programme on Recent Trends in AI and Machine Learning organized by Department of Information Technology, Delhi Technological University, Delhi from July 29-August 2, 2019.
3. Attended One Week TEQIP-III Sponsored Short Term Training Programme on Graph Theory and Its Applications organized by Department of Applied Mathematics, Delhi Technological University, Delhi from November 25-29, 2019.

(In Year: 2018)

1. Event Coordinator, Popular Lecture on “Low Pressure and Atmospheric Pressure Plasma Interactions with Molten Metals and Liquid Droplets for Materials Processing” by Prof. Mahendra K.Sunkara organized by DelTech Engineering Physics Technical Hub (DEPTH), Department of Applied Physics, Delhi Technological University held on Feb.6, 2018.
2. Attended One Week TEQIP-III Sponsored Faculty Development Programme on Emerging Trends in Internet of Things (IOT) and Cyber Security Applications in Smart Grid (EICS-2018) organized by Department of Electrical Engineering, Delhi Technological University, Delhi from March 12-16, 2018.

(In Year: 2017)

1. Organizing Committee Member, 2nd National Conference on Recent Developments in Electronics (NCRDE 2017) to be held on February 17-18, 2017. Jointly Organized by IEEE EDS Delhi Chapter and Department of Electronic Science, University of Delhi South Campus, Benito Juarez Road, New Delhi-110021, India
2. Jury Member, Project Presentation Session, 2nd National Conference on Recent Developments in Electronics (NCRDE 2017) to be held on February 17-18, 2017. Jointly Organized by IEEE EDS Delhi Chapter and Department of Electronic Science, University of Delhi South Campus, Benito Juarez Road, New Delhi-110021, India
3. Organizing Committee Member, 10th National Conference on Solid State Chemistry and Allied Areas (ISCAS-2017), held on July 1-3, 2017. Jointly Organized by Indian Association of Solid State Chemists and Allied Scientists and Department of Applied Physics, Delhi Technological University, India
4. Session Co-Chair, 10th National Conference on Solid State Chemistry and Allied Areas (ISCAS-2017), held on July 1-3, 2017. Jointly Organized by Indian Association of Solid State Chemists and Allied Scientists and Department of Applied Physics, Delhi Technological University, India

(In Year: 2016)

1. Attended a TEQIP-II Sponsored One Week Faculty Development Programme on Environmental Pollution: Monitoring and Control organized by Department of Environmental Engineering, Delhi Technological University, October 24- October 28, 2016.
2. Organizing Committee Member, Second National Conference on Recent Trends in Instrumentation and Electronics to be held on October 5th - 6th 2016. Shaheed Rajguru College of Applied Sciences for Women (University of Delhi) Vasundhara Enclave, Delhi – 110096.
3. Attended a one week workshop titled “E-Resources: A Gateway for Research” organized by Central Library, Delhi Technological University from September 5- September 9, 2016.
4. Convenor, TEQIP-II Sponsored One Week Faculty Development Programme on Advances in Microelectronics and Plasma Diagnostics organized by Department of Applied Physics, Delhi Technological University in association with IEEE EDS Delhi Chapter on August 29- September 2, 2016.
5. Member, Board of Advisory Committee, National Conference (IC GATE-2016), Manav Rachna University, June 2016.
6. Attended a one week TEQIP-II sponsored short term course on Recent Trends in Geoenvironmental Engineering organized by Delhi Technological University, Delhi during April 18-22, 2016.
7. Convenor, One Day National Seminar on Frontiers in Applied Science and Technology (FAST-2016) organized by Department of Applied Physics, Delhi Technological University in association with IEEE EDS Delhi Chapter on March 22, 2016.

(In Year: 2015)

1. Attended a two week TEQIP-II Sponsored Faculty Development Programme on Automation in Manufacturing (AIM-2015), organized by Department of Mechanical, Production and Industrial Engineering, Delhi Technological University, Delhi during May 4-15, 2015.
2. Attended a one day Synopsys University Symposium: Electronic System Design and Prototyping: Tools & Methodologies, Hotel Shangri La, New Delhi, April 30, 2015.
3. Coordinator, Two Day Workshop on Quadcopter UAV in association with IIT Guwahati, Delhi Technological University, April 24-25, 2015.
4. Attended One Week UGC Sponsored Short Term Training Programme on “The Idea Tree: Journey from Inception to Publication” organized by Department of Humanities, Delhi Technological University, Delhi during February 9-13, 2015.
5. Organizing Committee Member, UGC Sponsored One Day National Seminar on Recent Advances in   Physics (NSRAP-2015), Department of Applied Physics, Delhi Technological University, February 16, 2015
6. Coordinator, A National Level Championship: Workshop on Raspberry Pi in association with IIT-Bombay, Delhi Technological University, October 16-17, 2015.
7. Coordinator, Start Up Weekend Powered by Google for Entrepreneurs organized By E-Cell DTU, Delhi Technological University, Oct. 30-31 and Nov.1, 2015.
8. Attended a two-day National Workshop on Power Electronics (NWPE-2015), Department of Electrical Engineering, Delhi Technological University, November 6-7, 2015.
9. Attended a 7 day Management Capacity Enhancement Programme (MCEP), Indian Institute of Management, Indore, November 16-22, 2015.

(In Year: 2014)

1.   Attended a two weeks AICTE Sponsored Faculty Development Programme on “Information and  Cyber Security Management” held in G.B.Pant University of Agriculture and Technology, Pant Nagar, Uttarakhand, December 22^nd 2013-January 05^th, 2014.

2. Attended a One Day Seminar cum Workshop on nano-simulation using Atomistix Toolkit & Virtual Nanolab By Dr. Kurt Stokbro (CEO, QuantumWise) at USIC, Jawaharlal Nehru University, New Delhi on January 15, 2014

3. Attended One Week UGC Sponsored Short Term Training Programme on “Virtual Instrumentation Through ICT” organized by Computer Center, Delhi Technological University, Delhi during April 28- May 2, 2014.

4. Attended One Week TEQIP-II Faculty Development Programme on Modelling and Simulation of Dynamical Systems and Optimization (MSDSO-2014) organized by Department of Mechanical, Production and Industrial and Automobile Engineering, Delhi Technological University, Delhi during June 9-13, 2014.

5. Attended One Week TEQIP-II Faculty Development Programme on Renewable Energy and Alternative Fuels (REAF-2014) organized by Department of Mechanical, Production and Industrial and Automobile Engineering, Delhi Technological University, Delhi during June 16-20, 2014.

(In Year: 2013)

1.     Attended a one day workshop on Intellectual Property Rights and Patents organized by Delhi School of Management Delhi Technological University, held on March 8, 2013 at Administrative Building, Delhi Technological University, Delhi.

2. Attended a two day workshop on “Intellectual Property Rights meets IT-2^nd Series” organized jointly by Delhi School of Management and Department of Information Technology, Delhi Technological University, held on May 2-3, 2013 at Administrative Building, Delhi Technological University, Delhi.

3. Attended a two day workshop “National Workshop on Quality Assurance and Accreditation” held on 12-13 May’2013 at Hotel Ashoka, Chanakya Puri, New Delhi.

4. Attended the Faculty Day @ SAP Labs, Bangalore, June 14, 2013

5. Attended a one month Orientation Course (OR-74) held in Center for Professional Development in Higher Education (CPDHE), University of Delhi, North Campus, New Delhi, June 20^th-July 17^th, 2013.

6. Attended Indian Society for Technical Education (ISTE) Delhi Section Convention, held in Dr.B.R.Ambedkar Auditorium, Delhi Technological University, New Delhi, September 5^th-6^th, 2013.

7. Attended a one day National Instruments Technical Symposium held on September 20, 2013 at Essex Farms, New Delhi

8.  Convener, One Day Seminar on “New Frontiers in Physics for Society” held on September 24, 2013, at Administrative Building, Delhi Technological University, Delhi.

1. Convener, Two-Day Workshop on MATLAB held on September 28-29, 2013, at Committee Room, Science Block, 1^st Floor, Delhi Technological University, Delhi.
2. Convener, Two Day Workshop on Ethical Hacking held on October 4-5, 2013, at Administrative Building, Delhi Technological University, Delhi.
3. Convener, One Day B-Plan Workshop- ‘Cerebrations’ organized by E-Cell, DTU held on October 28, 2013, at Administrative Building, Delhi Technological University, Delhi.
4. Attended One Week UGC Sponsored Short Term Training Programme on “Signal Processing in Modern Electrical Systems” organized by Department of Electrical Engineering, Delhi Technological University, Delhi during December 9-13, 2013.

(In Year: 2012)

1.  Attended a Two Day Workshop on Experiments & Research Applications with National Instruments LabView organized by Bhaskaracharya College of Applied Sciences in collaboration with Trident TechLabs Pvt.Ltd, February 2-3 2012, Bhaskaracharya College of Applied Sciences, University of Delhi, India.

2. Attended One Day National Seminar cum Workshop on Mathematics and Computing, organized by Department of Applied Mathematics, Delhi Technological University, held on March-22, 2012 at Administrative Building, Delhi Technological University, Delhi.

3. Attended a Two Day workshop on Recent Advances in Software Engineering, organized by Department of Computer Engineering, Delhi Technological University, held on April 20-April 21, 2012 at Administrative Building, Delhi Technological University, Delhi.

4.     Attended a one day Mail Today Education Conclave 2012: Making Public Private Partnership Work for Higher Education, Hotel Shangri La, Connaught Place, New Delhi, August 25, 2012.

       5.     Attended a Two Day 7th All India Students’ Conference on Science and Spiritual Quest organized by Bhaktivedanta Institute, Kolkatta, J.N.Tata Auditorium, IISc Bangalore, India held on September 1-2, 2012.            

(In Year: 2011)

1. Attended Three Day Joint Academies Lecture Workshop on Frontiers in Physics, jointly organized by IEEE Delhi Chapter, Indian Academy of Science, Bangalore, National  Academy of Science, Allahabad and Indian National Science Academy, New Delhi, January 21-23, 2011 at S.P.Jain Center, South Campus, University of Delhi, Dhaula Kuan, India
2. Attended One Day IEEE-EDS Technical Conference on Silvaco TCAD Package from Silvaco International, April 19, 2011 at Arts Faculty, South Campus, University of Delhi, Dhaula Kuan, India.
3. Member- Organizing Committee: National Seminar on Recent Advances in Microelectronic Devices, sponsored By Defence Research and Development Organization, Ministry of Defence, Government of India, August 19-20, 2011, held at Maharaja Agrasen Institute of Technology, Guru Gobind Singh Indraprastha University, New Delhi
4. Attended Two Day Conference on Recent Trends in Synthesis and Application of Advanced Materials (RTSAAM 2011), 5-6 December 2011, Maharaja Agrasen Institute of Technology, GGSIPU, New Delhi, India.

(In Year: 2010)

1. Member- Organizing Committee: Second National Workshop on Recent Trends in Semiconductor Devices and Technology, Sponsored By Integrated Microsystem, India, and Society for Microelectronics and VLSI, New Delhi, September 17-18, 2010 held at Deen Dayal Upadhyaya College, University of Delhi, New Delhi.
2. Member- Organizing Committee: First National Workshop on Recent Trends in Semiconductor Devices and Technology, Sponsored By Integrated Microsystem, India, and Society for Microelectronics and VLSI, New Delhi, February 12-13, 2010 held at Deen Dayal Upadhyaya College, University of Delhi, New Delhi.
3. Member- Organizing Committee: Third National Conference on Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2010), Sponsored By IEEE EDS-Delhi Chapter and Society for Microelectronics and VLSI, New Delhi, January 30-31, 2010 held at Convention Hall, North Campus, University of Delhi, New Delhi.

(In Year: 2009)

1. Member- Organizing Committee: Two-Day National Workshop on Fiber Optics and Applications, Sponsored By Delhi Chapter-National Academy of Sciences, India, November 28-29, 2009, held at Deen Dayal Upadhyaya College, University of Delhi, New Delhi.
2. Member- Organizing Committee: Second One-Day National Workshop on Einstein & Special Theory of Relativity, Sponsored By Delhi Chapter-National Academy of Sciences, India, November 07, 2009, held at Deen Dayal Upadhyaya College, University of Delhi, New Delhi.
3. Member- Organizing Committee: First One-Day National Workshop on Einstein & Special Theory of Relativity, Sponsored By Delhi Chapter-National Academy of Sciences, India, November 06, 2009, held at Deen Dayal Upadhyaya College, University of Delhi, New Delhi.
4. Member- Organizing Committee: Three days Workshop on “Futuristic trends of Quality Control in Information Security Management”, Sponsored by CSIR, Govt. of India, October 09-11, 2009 organized by Forum for Interdisciplinary Application in Sciences (FiDAS) Deen Dayal Upadhyaya College, University of Delhi, New Delhi.
5. Attended a one week WORKSHOP ON OPEN EDUCATIONAL RESOURCES (WIKIEDUCATOR) Organized by University of Delhi South Campus and Acharya Narendra Dev College With support from the Commonwealth of Learning, Vancouver, Canada from April 13-17, 2009 at University of Delhi South Campus, New Delhi
6. Attended a one week workshop on “EASY NOW - WORKSHOP ON MULTIMEDIA CONTENT DEVELOPMENT” Organized by Acharya Narendra Dev College and Commonwealth Educational Media Centre for Asia from April 20 - 25, 2009 in Acharya Narendra Dev College, Kalkaji, New Delhi

(In Year: 2007)

1. Attended the IMS Conference 2007 “Trends in VLSI Design and Embedded Systems” held on 17^th-18^th August, 2007 at Chandigarh and presented a paper entitled “New Concave MOSFET with Transverse Dual Material Gate (T-DMG) in Sub-50nm regime”.

(In Year: 2006)

1. Attended the National Conference on Recent Advancements in Microwave Technique and Applications (Microwave-2006) held on 06^th-08^th October, 2006 at Jaipur and presented a paper entitled “Exploring the Effect of Negative Junction Depth on Electrical Behaviour of Sub-50-Nanometer Concave DMG MOSFET: A Simulation Study”.
2. Attended the National Conference on Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2006) held at Deen Dayal Upadhyaya College, University of Delhi, New Delhi, India from 24^th -26^th March 2006 and presented a paper entitled “Design and FPGA realization of Direct Sequence-Spread Spectrum (DS-SS) BPSK Modulator using a Five Stage Gold Code Generator”.
3. Participated in a National Workshop on VLSI Design and Embedded Systems (NWVDES) held at Birla Institute of Technology and Science, Pilani from 24^th-26^th February, 2006.

(In Year: 2005)

1. Attended a short course on “Spice Models for Advanced VLSI Circuit Simulation (SMAVCS)” organized by Department of Electronic Science, University of Delhi South Campus, New Delhi, India form 11^th-12^th December, 2005.

At Delhi Technological University :

1. Director- Vinod Dham Centre of Excellence for Semiconductors and Microelectronics
2. Associate Dean (Acad-UG) (2024-Till Date)
3. Faculty In-Charge-Day Care Centre (2019-Till Date)
4. Associate Dean (Acad-PG) (2019-2022)
5. Faculty Advisor of DEPTH (Deltech Engineering Physics Technological Hub), Undergraduate Society that has members from all branches of Engineering Mechanical, Civil, Electronics etc).The society holds various Lectures, Group Discussions, Workshops on topics ranging from Semiconductor Devices, Nanotechnology to Robotics, Android Application Development.
6. Faculty Placement Coordinator for B.Tech-Engineering Physics.
7. Faculty Advisor, E-Cell, DTU.
8. Faculty Advisor of E-Summit-2012, E-Summit-2013 and E-Summit-2014 (Entrepreneurship Summit) (Annual Entrepreneurship event, Delhi Technological University).
9. Faculty Advisor of Aurora-2014, 2016 and 2017(Technical Fest of Engineering Physics Society)
10. Member, Organizing Team-Global Alumni Conclave 2012 and Global Alumni Conclave 2013 (Annual Alumni Event, Delhi Technological University)
11. Member-Conduct of Elections of President/VP/Secretary-Students Association DTU, 2012
12. Member, Core Committee, Global Alumni Conclave-2012, DTU
13. Member, Finance and Account Committee, Global Alumni Conclave-2012, DTU
14. Member, Sponsorship Committee, Global Alumni Conclave-2012, DTU
15. Member, Hospitality and Publicity Committee, Global Alumni Conclave-2012, DTU
16. Member, Event Management Committee, Global Alumni Conclave-2012, DTU
17. Member, Core Committee, Global Alumni Conclave-2013, DTU
18. Member, Invitation Committee, Global Alumni Conclave-2013, DTU
19. Member, Sponsorship Committee, Global Alumni Conclave-2013, DTU
20. Member, Hospitality and Publicity Committee, Global Alumni Conclave-2013, DTU
21. Member, Event Management Committee, Global Alumni Conclave-2013, DTU
22. Coordinator-Information and Development, Deptt. Of Applied Physics (2010-2012 and 2016-Till Date)
23. Coordinator-B.Tech-Engg.Physics-III-IV Sem (2013)
24. Member-Board of Studies, Deptt. Of Applied Physics (2010-2012)
25. Member-Board of Studies, Deptt. Of Mechanical Engg. For Interdepartmental course of M.Tech (Renewable Energy Technology)-2013.
26. Member-Board of Studies, Deptt. Of Applied Physics (2018-Till Date)
27. Member, Physical Verification Committee, Dept. of Training and Placement (2012)
28. Member, Physical Verification Committee, Dept. of Training and Placement (2013)
29. Member, Results Preparation Committee, Ph.D Admissions, 2012
30. Member, Results Preparation Committee, Ph.D Admissions, 2013
31. Member, Organizing Committee, Technical Fest-2013
32. Member, Stationary and Printing Purchase Committee, DTU (2013-2014)
33. Expert Within the Deptt. for SRC of Department of Applied Physics
34. Expert Outside the Deptt. For SRC of Department of ECE and COE
35. Member, Scrutiny Cum Screening Committee for Assistant Professor on Contractual basis (2014)
36. Expert Outside the Deptt. For SRC of Department of EE.
37. Member, Departmental Purchase Committee, 2016-till date
38. Deputy Coordinator, Supplementary Examination Evaluation (November 2016)
39. Deputy Coordinator, Supplementary Examination Evaluation (February 2017)
40. Deputy Coordinator, Supplementary Examination Evaluation (February 2018)
41. Deputy Coordinator, End Term Examination Evaluation (May 2017)
42. Deputy Coordinator, End Term Examination Evaluation (May 2018)
43. DPC Member-Purchase Committee under TEQIP-III (2018)
44. Deputy Chairperson, QIP Ph.D Admissions-2020-2022.
45. ?Coordinator-AEC/VAC/SEC (2023-Till Date)
46. Deputy Coordinator, End Term Examination Evaluation (Nov./Dec 2023)

Research Publiications in SCIE

1. Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, “Performance Investigation of 50nm Insulated Shallow Extension Gate Stack (ISEGaS) MOSFET for Mixed Mode Applications,” IEEE Transactions on Electron Devices, Vol. 54, No.2, pp. 365-368, February 2007. (IF: 2.913)

2. Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, “Unified Subthreshold Model for Channel Engineered Sub-100nm Advanced MOSFET Structures”, IEEE Transactions on Electron Devices, Vol.54, No.9, pp.2475-2486, September 2007. (IF: 2.913)

3. Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, “Hot carrier reliability and analog performance investigation of DMG-ISEGaS MOSFET”, IEEE Transactions on Electron Devices, Vol. 54, No.9, pp.2556-2561, September 2007. (IF: 2.913)

4. Ravneet Kaur, Rishu Chaujar, Manoj Saxena, and R. S. Gupta, “Two-Dimensional Analytical Model to Characterize Novel MOSFET Architecture: Insulated Shallow Extension (ISE) MOSFET”, Semiconductor Science and Technology, Vol.22,No.8, pp.952-962, August 2007. (IF: 2.65)

5. Ravneet Kaur, Rishu Chaujar, Manoj Saxena, and R. S. Gupta, “Lateral Channel Engineered - Hetero Material Insulated Shallow Extension Gate Stack (HMISEGAS) MOSFET Structure: High Performance RF Solution for MOS Technology ”, Semiconductor Science and Technology, Vol.22, No.10, pp. 1097-1103, October 2007. (IF: 2.65)

6. Sona P.Kumar, Anju Agrawal, Rishu Chaujar, Sneha Kabra, Mridula Gupta and R. S. Gupta, “Threshold Voltage Model for Small Geometry AlGaN/GaN HEMTs Based on Analytical Solution of 3-D Poisson’s Equation,” Microelectronics Journal, Vol.38, No.10-11, pp.1013-1020, October-November 2007. (IF: 1.605)

7. Sona P.Kumar, Anju Agrawal, Rishu Chaujar, Mridula Gupta and R. S. Gupta, “Analytical Modeling and Simulation of Subthreshold Behavior in Nanoscale Dual Material Gate AlGaN/GaN HEMT”, Superlattices and Microstructures, Vol.44, pp.37-53, July, 2008. (IF: 2.658)

8. Sona P.Kumar, Anju Agrawal, Rishu Chaujar, Mridula Gupta and R. S. Gupta, “Performance Assessment and Sub-Threshold Analysis of Gate Material Engineered AlGaN/GaN HEMT For Enhanced Carrier Transport Efficiency”, Microelectronics Journal, Vol.39, No.12, pp.1416-1424, December, 2008. (IF: 1.605)

9. Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, “TCAD Assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and its Multi-Layered Gate Architecture: Part-I: Hot Carrier Reliability Evaluation”, IEEE Transactions on Electron Devices, Vol.55, No.10, pp. 2602-2613, 2008. (IF: 2.913)

10. Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, “Laterally amalgamated DUal Material GAte Concave (L-DUMGAC) MOSFET For ULSI”, Microelectronic Engineering, Vol. 85, No. 3, pp. 566-576, March 2008. (IF: 2.523)

11. Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, “Two-Dimensional Analytical Sub-Threshold Model of Multi-Layered Gate Dielectric Recessed Channel (MLaG-RC) Nanoscale MOSFET”, Semiconductor Science and Technology, Vol.23, No.4, April, 2008. (IF: 2.65)

12. Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, “Intermodulation Distortion and Linearity Performance Assessment of 50-nm gate length L-DUMGAC MOSFET for RFIC Design”, Superlattices and Microstructures, Vol.44, pp.143-152, 2008. (IF: 2.658)

13. Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, “Investigation of Multi-Layered-Gate Electrode Workfunction Engineered Recessed Channel (MLGEWE-RC) Sub-50nm MOSFET: A Novel Design”, International Journal of Numerical Modeling: Electronic Networks, Devices and Fields, Vol.20, pp.259-278, October 2008. (IF: 1.296)

14. Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, “On-State and RF Performance Investigation of Sub-50nm L-DUMGAC MOSFET Design for High-Speed Logic and Switching Applications”, Semiconductor Science and Technology, Vol.23, No.9, September, 2008. (IF: 2.65)

15. Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, “Two-dimensional threshold voltage model and design considerations for gate electrode workfunction engineered recessed channel (GEWE-RC) nanoscale MOSFET: part 1”, Semiconductor Science and Technology, Vol.24, No.6, 10pp, June, 2009. (IF: 2.65)

16. Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, “TCAD assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and its multi-layered gate architecture, Part II: Analog and large signal performance evaluation”, Superlattices and Microstructures, Volume 46, Issue 4, Pages 645-655, October 2009. (IF: 2.658)

17. Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, “Two-Dimensional Simulation and Analytical Modeling of a Novel ISE MOSFET with gate stack configuration”, Microelectronic Engineering, Vol.86, pp.2005-2014, 2009. (IF: 2.523)
18. Ravneet Kaur, Rishu Chaujar, Manoj Saxena, and R. S. Gupta, “Hot Carrier Reliability Monitoring of DMG ISE SON MOSFET for Improved Analog Performance”, Microwave and Optical Technology Letters, Vol.52, No.3, pp. 770-775, 2010. (IF: 1.392)

19. Pujarini Ghosh, Rishu Chaujar, Subhasis Haldar, R.S Gupta and Mridula Gupta, “Analytical Modeling of Channel Noise for Gate Material Engineered Surrounded/Cylindrical Gate (SGT/CGT) MOSFET”, Special Issue of Journal of World Academy of Science, Engineering and Technology, Issue 64, pp. 615-618, April 2010.

20. Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, “Design Considerations and Impact of Technological Parametric Variations on RF/Microwave Performance of  GEWE-RC MOSFET”, Microwave and Optical Technology Letters, Vol.52, No.3, pp.652-657, 2010. (IF:1.392)
21. Priyanka Malik, Sona P.Kumar, Rishu Chaujar, Mridula Gupta and R. S. Gupta, “Gate Material Engineered-Trapezoidal Recessed Channel MOSFET (GME-TRC) for High Performance Analog and RF Applications”, Microwave and Optical Technology Letters, Vol.52, No.3, pp.694-698, 2010. (IF: 1.392)
22. Priyanka Malik, Rishu Chaujar, Mridula Gupta and R.S Gupta, “Two-dimensional Analytical Drain Current Model for Multilayered-Gate Material Engineered Trapezoidal Recessed Channel (MLGME-TRC) MOSFET: a Novel Design”, Special Issue of Journal of World Academy of Science, Engineering and Technology, Issue 64, pp. 472-476, April 2010.
23. Priyanka Malik, Rishu Chaujar, Mridula Gupta and R.S.Gupta,"Physics based Threshold Voltage Analysis of Gate Material Engineered Trapezoidal Recessed Channel (GME-TRC) nanoscale MOSFET and its multilayered gate architecture", International Journal of Microwave and Optical Technology ( IJMOT), pp.361-368, Vol.5, No.6, November 2010.
24. Sona P.Kumar, Anju Agrawal, Rishu Chaujar, Mridula Gupta and R. S. Gupta, “Device Linearity and Intermodulation Distortion Comparison of Dual Material Gate and Conventional AlGaN/GaN High Electron Mobility Transistor”, Microelectronics Reliability, pp.587-596, Vol.51, March 2011. (IF: 1.589)
25. Priyanka Malik, R.S.Gupta, Rishu Chaujar and Mridula Gupta, “Linearity-Distortion analysis of GME-TRC MOSFET for High Performance and Wireless Applications”, Journal of Semiconductor Technology and Science, pp.162-174, Vol.11, No.3, September 2011.
26. Priyanka Malik, R.S.Gupta, Rishu Chaujar and Mridula Gupta, “AC Analysis of nanoscale GME-TRC MOSFET for Microwave and RF Applications”, Microelectronics Reliability, pp.151-158, Vol.52, Issue 1, January 2012. (IF: 1.589)
27. Ajita Agrawala and Rishu Chaujar, “Noise Analysis of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET”, Journal of Physics-Conference Series, Vol. 367 012013, pp. 8 pages, 2012.
28. Ajita Agarwala and Rishu Chaujar, “Frequency Dependence of Noise Performance Metrices for Gate Electrode Work Function Engineered Recessed Channel MOSFET”, International Journal of Information and Electronics Engineering, Vol.3(4), pp.432-435, 2013.
29. Mohit Gupta, and Rishu Chaujar, “Implementing True Zero Cycle Branching in Scalar and Superscalar Pipelined Processors”,    ACEEE International Journal of Information Technology 3(3):6 (September 2013)
30. Jaya Madan, R.S.Gupta and Rishu Chaujar, “Influence of Heterogeneous Gate Dielectric on Hetero-Dielectric-DMG-GAATFET for Improved tunneling current”, International Journal of Advanced Technology in Engineering and Science, 2(1), pp.41-47, September, 2014. (IF: 2.870)
31. Neha Gupta, Ajay Kumar and Rishu Chaujar, “Investigation of Frequency Dependent Parameter of GEWE-SiNW MOSFET for Microwave and RF Applications”, International Journal of Advanced Technology in Engineering and Science, 2(1), pp.35-40, September, 2014. (IF: 1.012)
32. Rahul Pandey and Rishu Chaujar, “Enhanced Back-Contact Back Junction Crystalline Silicon Solar Cell Performance with Silicon Carbide (SiC) Based Front Surface Passivation”, International Journal of Advanced Technology in Engineering and Science, 2(1), pp.626-630, September, 2014. (IF: 1.012)
33. Anuj Kumar Sinha and Rishu Chaujar, “Luminous TCAD Analysis of Transparent ITO Gate Recessed Channel MOSFET using Elliptical Lenslet”, International Journal of Computer Applications in Engineering Sciences, pp:17-25, Vol.IV, Special Issue, September 2014 (IF:0.395)
34. Ajay Kumar, Neha Gupta and Rishu Chaujar, “Investigation of Frequency Dependence on the Noise Response of a Novel Transparent Gate Recessed Channel MOSFET”, International Journal of Electrical and Electronics Engineers, IJEEE, Vol.No.6, Issue No.2, pp.:07-13, July-Dec, 2014.
35. Neha Gupta, Ajay Kumar and Rishu Chaujar, “Impact of Device Parameter Variation on RF performance of Gate Electrode Workfunction Engineered (GEWE)-Silicon Nanowire (SiNW) MOSFET”, Journal of Computation Electronics, Springer, Vol. 14, Issue 3, pp.798-810, September 2015. (IF: 1.807)
36. Jaya Madan, R.S. Gupta and Rishu Chaujar, “Analytical Drain Current Formulation for Gate  Dielectric Engineered Dual Material Gate-Gate All Around-Tunneling Field Effect Transistor”, Japanese Journal of Applied Physics, Vol.54, 094202-1:094202-9, 2015. (IF: 1.48)
37. Ajay Kumar, Rishu Chaujar and Neha Gupta, “Analysis of Novel Transparent Gate Recessed Channel (TGRC) MOSFET for Improved Analog Behaviour”, Microsystem Technologies, Springer, Vol.22, pp.2665-2671, November, 2016. (IF: 2.276)
38. Rahul Pandey and Rishu Chaujar, “Novel Back-Contact Back Junction SiGe (BC-BJ SiGe) Solar Cell for Improved Power Conversion Efficiency”, Microsystem Technologies, Springer, Vol.22, pp.2673-2680, November, 2016.  (IF: 2.276)

39. Ajay Kumar, Neha Gupta and Rishu Chaujar, ^“TCAD RF Performance Investigation of Transparent Gate Recessed Channel MOSFET”, Vol.49, pp.36-42, Microelectronics Journal, Elsevier, 2016. (IF: 1.605)

40. Ajay Kumar, Neha Gupta and Rishu Chaujar, ^“Power gain assessment of ITO based Transparent Gate Recessed Channel (TGRC) MOSFET for RF/wireless applications”, Vol.91, pp.290-301, Superlattices and Microstructures, Elsevier, 2016. (IF: 2.658)

41. Jaya Madan and Rishu Chaujar, “Interfacial Charge Analysis of Heterogeneous Gate Dielectric - Gate All Around - Tunnel FET for Improved Device Reliability," IEEE Transactions on Device and Materials Reliability, Vol.16, Issue 2, pp. 227-234, May 2016. (IF: 1.76)

42. Rahul Pandey and Rishu Chaujar, “Rear contact SiGe solar cell with SiC passivated front surface for >90-percent external quantum efficiency and improved power conversion efficiency”, Solar Energy, Elsevier, Vol.135, pp.242-252, October 2016. (IF:5.742).

43. Neha Gupta and Rishu Chaujar, “Influence of Gate Metal Engineering on Small Signal and Noise Behaviour of Silicon Nanowire MOSFET for Low Noise Amplifiers” Applied Physics A, Springer, Vol.122 (8), pp. 717 (1-9), 2016. (IF: 2.584)

44. Neha Gupta and Rishu Chaujar, “Optimization of High-k and Gate Metal Workfunction for Improved Analog and Intermodulation Performance of Gate Stack (GS)-GEWE-SiNW MOSFET”, Superlattices and Microstructure, Elsevier, Vol.97, pp.630-641, 2016. (IF: 2.658)

45. Neha Gupta and Rishu Chaujar, “Investigation of temperature variations on Analog/RF and Linearity Performance of Stacked Gate GEWE-SiNW MOSFET for improved device reliability”, Microelectronics Reliability, Elsevier, Vol.64, pp.235-241, September 2016. (IF: 1.589)

46. Rahul Pandey and Rishu Chaujar, “Front Surface Passivation Scheme for Back-Contact Back-Junction (BC-BJ) Silicon Solar Cell”, Advanced Science Letters, 22, 815-820, 2016

47. Rahul Pandey and Rishu Chaujar, “Numerical simulation of rear contact silicon solar cell with a novel front surface design for the suppression of interface recombination and improved absorption”, Current Applied Physics, Vol.16, pp.1581-1587, 2016. (IF: 2.48)

48. Rahul Pandey and Rishu Chaujar, “Numerical simulations: Toward the design of 27.6% efficient four-terminal semi-transparent perovskite/SiC passivated rear contact silicon tandem solar cell”, Superlattices and Microstructure, Elsevier, Vol.100, pp.656-666, Dec. 2016. (IF: 2.658)                                                                                                             

49. Jaya Madan and Rishu Chaujar, “Gate Drain Overlapped - Asymmetric Gate Dielectric - GAA - TFET: A Solution for Suppressed Ambipolarity and Enhanced ON-State Behavior”, Applied Physics-A, 122:973, DOI 10.1007/s00339-016-0510-0, 2016. (IF: 2.584)

50. Neha Gupta, Ajay Kumar and Rishu Chaujar, “Oxide Bound Impact on Hot Carrier Degradation for Gate Electrode Workfunction Engineered (GEWE) Silicon Nanowire MOSFET”, Microsystem Technologies, Springer, Vol.22, pp2655-2664, November, 2016. (IF: 2.276)

51. Jaya Madan and Rishu Chaujar, “Palladium gate all around - Hetero dielectric -tunnel FET based highly sensitive hydrogen gas sensor”, Superlattices and Microstructures, Vol.100, pp. 401-408, December 2016. (IF: 2.658)

52. Neha Gupta and Rishu Chaujar, “Quantum Analysis Based Extraction of Frequency Dependent Intrinsic and Extrinsic Parameters for GEWE-SiNW MOSFET”, Journal of Computation Electronics, Springer, Vol.16, Issue.1, pp.61-73, March 2017. (IF: 1.807)

53. Jaya Madan and Rishu Chaujar, “Gate Drain Underlapped-PNIN-GAA-TFET for Comprehensively Upgraded Analog/RF Performance”, Superlattices and Microstructures, Vol.102, pp. 17-26, February 2017. (IF: 2.658)

54. Jaya Madan, R. S. Gupta and Rishu Chaujar, "Performance Investigation of Heterogeneous Gate Dielectric-Gate Metal Engineered-Gate All Around-Tunnel FET for RF Applications", Microsystem Technologies, Vol.23, Issue 9, pp.4081-4090, September, 2017. (IF: 2.276)

55. Ajay Kumar, Neha Gupta and Rishu Chaujar, “Effect of Structured Parameters on Hot-Carrier Immunity of Transparent Gate Recessed Channel (TGRC) MOSFET”, Microsystem Technologies, Springer, Vol.23, Issue 9, pp.4057-4064, September, 2017 (IF: 2.276).
56. Jaya Madan, R. S. Gupta and Rishu Chaujar, “Mathematical modeling insight of hetero gate dielectric dual material gate GAA tunnel FET for VLSI/analog applications,” Microsystem Technologies, Springer, Vol.23, Issue 9, pp.4091-4098, September, 2017. (IF: 2.276)

57. Jaya Madan and Rishu Chaujar, “Numerical Simulation of N+ Source Pocket PIN- GAA - Tunnel FET: Impact of Interface Trap Charges and Temperature Affectability”, vol. 64, pp. 1482-1488, IEEE Transactions on Electron Devices, 2017. (IF: 2.913)

58. Rahul Pandey and Rishu Chaujar “TCAD Design of 29.5% Efficient Perovskite/ IBC-SiHJ Mechanically-Stacked Tandem Solar Cell for Energy Efficient Applications”, Journal of Photonics for Energy, SPIE, vol. 7(2), pp. 022503:1-022503:13, April-June 2017. (IF: 1.836)

59. Samit Ganguli and Rishu Chaujar, “Newly Designed Audio Manipulator for Improved Performance and Accuracy”, International Journal of Trend in Research and Development, ISSN: 2394-9333, Vol.4, Issue 1, pp. 450-451, January-February 2017. (IF: 4.004).

60. Ajay Kumar, MM Tripathi, and Rishu Chaujar, ^“Investigation of Parasitic Capacitances of In₂O₅Sn Gate Electrode Recessed Channel MOSFET for ULSI Switching Applications” Microsystem Technologies, Springer, Vol.23, pp. 5867-5874, 2017. (IF: 2.276)

61. R. Pandey and R. Chaujar, "Numerical simulations of novel SiGe-based IBC-HJ solar cell for standalone and mechanically stacked tandem applications," Materials Research Bulletin, vol. 93, pp. 282-289, 9// 2017. (IF: 4.64)

62. Jyoti Shah, Saood Ahmad, Rishu Chaujar, Nitin K.Puri, P.S.Negi and R.K.Kotnala, “Role of Magnetic Exchange Interaction due to Magnetic Anisotropy on Inverse Spin Hall Voltage at FeSi_3%/Pt Thin Film Bilayer Interface”, Journal of Magnetism and Magnetic Materials, Elsevier, Vol.443, pp. 159-164, Dec. 2017. (IF: 2.99)

63. Jaya Madan and Rishu Chaujar, “Temperature Associated Reliability Issues of Heterogeneous Gate Dielectric - Gate All Around - Tunnel FET”, IEEE Transactions on Nanotechnology, Vol.17, Issue 1, pp.41-48, Jan 2018. (IF: 2.57)

64. Ajay Kumar, MM Tripathi, and Rishu Chaujar, “Reliability Issues of In₂O₅Sn Gate Electrode Recessed Channel MOSFET: Impact of Interface Trap Charges and Temperature” IEEE Transactions on Electron Devices, Vol.65, No.3, pp.860-863, 2018. (IF: 2.913)

65. Ajay Kumar, MM Tripathi, and Rishu Chaujar, “Comprehensive analysis of sub-20?nm black phosphorus based junctionless-recessed channel MOSFET for analog/RF applications”, Vol.116, pp.171-180, Superlattices and Microstructures, February 2018. (IF: 2.658)

66. Ajay Kumar, MM Tripathi, and Rishu Chaujar, “In2O5Sn Based Transparent Gate Recessed Channel MOSFET: RF Small-Signal Model for Microwave Applications”, International Journal of Electronics and Communications (93), pp.233-241, 2018. (IF: 3.183)

67. Rahul Pandey and Rishu Chaujar, “Rear Contact Silicon Solar Cells with a-SiCX:H Based Front Surface Passivation for Near-Ultraviolet Radiation Stability”, Superlattices and Microstructures, Volume 122, Pages 111-123, October 2018. (IF: 2.658)

68. Jaya Madan, Rahul Pandey and Rishu Chaujar, “Gate Drain Underlapping: A Performance Enhancer for HD-GAA-TFET”, Materials Today Proceedings, Elsevier, Vol.5, pp.17453-17463, 2018.

69. Henika Arora, Jaya Madan and Rishu Chaujar, “Impact on Analog and Linearity Performance of Nanoscale AlGaN/GaN HEMT with variation in Surface Passivation Stack”, Materials Today Proceedings, Elsevier, Vol.5, pp.17464-17471, 2018.

70. Ajay Kumar, MM Tripathi, and Rishu Chaujar, “Ultra-Low Power Dielectric Modulated Nano-gap Embedded Sub-20nm TGRC-MOSFET for Biosensing Application”, Journal of Computational Electronics, Springer, Volume 17, Issue 4, pp 1807–1815, December 2018. (IF: 1.807)

71. Ajay Kumar, Samarth Singh, Balark Tiwari, MM Tripathi, and Rishu Chaujar “Radiation Analysis of N-Channel TGRC-MOSFET: An X-Ray Dosimeter”, IEEE Transactions on Electron Devices, Vol.65, Issue.11, pp.5014-5020, November 2018.(IF:2.913)

72. Skanda Shekhar, Jaya Madan and Rishu Chaujar, “Source/Gate Material Engineered Double Gate TFET for Improved RF and Linearity Performance: A Numerical Simulation”, Applied Physics-A, vol. 124, p.739, 2018. (IF: 2.584)

73. Ajay Kumar, Neha Gupta, M.M.Tripathi and Rishu Chaujar, “RF Noise Modeling of Black Phosphorus Junctionless Trench MOSFET in Strong Inversion Region”, Vol.125, pp.72-79, January, Superlattices and Microstructures, 2019 (IF: 2.658)

74. Rahul Pandey, Anand Prakash Saini and Rishu Chaujar, “Numerical simulations: Toward the design of 18.6% efficient and stable perovskite solar cell using reduced cerium oxide based ETL”, Vacuum, Elsevier, Vol.169, pp.173-181, 2019. (IF: 3.627)

75. Rishu Chaujar, “Analog and RF assessment of sub-20?nm 4H-SiC trench gate MOSFET for high frequency applications”, AEU - International Journal of Electronics and Communications, Volume 98, Pages 51-57, January 2019.(IF: 3.183)

76. Anuj Chhabra, Ajay Kumar and Rishu Chaujar, “Sub-20?nm GaAs junctionless FinFET for biosensing application”, Vacuum, Volume 160, February 2019, Pages 467-471. (IF: 3.627)

77. Rahul Pandey, Anu Singla, Jaya Madan, Rajnish Sharma and Rishu Chaujar, "Toward the design of monolithic 23.1% efficient hysteresis and moisture free perovskite/c-Si HJ tandem solar cell: A numerical simulation study", Journal of Micromechanics and Microengineering, (IOP), Vol. 29, pp.064001 (9pp) 2019.  (IF: 1.88)

78. A. Kumar, M. M. Tripathi and R. Chaujar, “Sub-30nm In₂O₅Sn gate electrode recessed channel MOSFET: A biosensor for Early Stage Diagnostics” Vacuum, Elsevier. Vol. 164, pp. 46-52, 2019. DOI: 10.1016/j.vacuum.2019.02.054. (IF: 3.627)

79. Jaya Madan, Rahul Pandey, Rajnish Sharma and Rishu Chaujar, “Impact of Metal Silicide Source Electrode on Polarity Gate Induced Source in Junctionless TFET”, Applied Physics-A (Springer), 125, Article no: 600, 2019. (IF: 2.584)

80. Ardaman Kaur, Rishu Chaujar, Vijayakumar Chinnadurai, “Effects of Neural Mechanisms of Pretask Resting EEG Alpha Information on Situational Awareness: A Functional Connectivity Approach”, Human Factors: The Journal of the Human Factors and Ergonomics Society, 2019 (Accepted) (IF: 4.17)

81. Ajay Kumar, Neha Gupta, M. M. Tripathi and Rishu Chaujar, “Analysis of Structural Parameters on Sensitivity of Black Phosphorus Junctionless Recessed Channel MOSFET for Biosensing Application”, in Microsystem Technologies, Vol.26, pp.2227-2233, Springer, 2020. DOI: 10.1007/s00542-019-04545-6. (IF: 2.276)

82. Neha Gupta, Ajay Kumar and Rishu Chaujar, “Design Considerations and Capacitance Dependent Parametric Assessment of Gate Metal Engineered SiNW MOSFET for ULSI Switching Applications”, Vol.12, pp. 1501-1510, Silicon (Elsevier), 2020. (IF: 2.67)

83. Ajay Kumar, Neha Gupta, Shrey Kumar Tripathi, M.M.Tripathi and Rishu Chaujar, “Performance evaluation of linearity and intermodulation distortion of nanoscale GaN-SOI FinFET for RFIC design”, AEU - International Journal of Electronics and Communications, Volume 115, February 2020, 153052. (IF: 3.183)

84. Jaya Madan, Minaxi Dassi, Rahul Pandey, Rishu Chaujar, Rajnish Sharma, “Numerical analysis of Mg2Si/Si heterojunction DG-TFET for low power/high performance applications: Impact of non- idealities”, Superlattices and Microstructures, Volume 139, 106397, March 2020. (IF: 2.658)

85. Ajay Kumar, Manan Roy, Neha Gupta, MM Tripathi, Rishu Chaujar,  “Dielectric modulated transparent gate thin film transistor for biosensing applications”, Materials Today: Proceedings, Volume 28, Part 1, 2020, Pages 141-145.

86. Ajay Kumar, Amit Kumar Goyal, Uddeshya Gupta, Tanya, Neha Gupta and Rishu Chaujar, “Increased efficiency of 23% for CIGS solar cell by using ITO as front contact”, Materials Today: Proceedings, Volume 28, Part 1, Pages 361-365, 2020

87. Ardaman Kaur, Vijayakumar Chinnadurai, Rishu Chaujar, “Microstates-based resting frontal alpha asymmetry approach for understanding affect and approach/withdrawal behaviour”, Scientific Reports, Volume 10, Article number: 4228 (2020). (IF: 4.37)

88. PM Tripathi, H Soni, R Chaujar and A Kumar, “Numerical Simulation and Parametric Assessment of GaN Buffered Trench Gate MOSFET for Low Power Applications”, IET Circuits, Devices & Systems, Volume 14, Issue 6, September 2020, p. 915 – 922. (IF: 1.29)

89. Jaya Madan, Rahul Pandey, Rajnish Sharma, Rishu Chaujar, “Investigation of electrical/analog performance and reliability of gate metal and source pocket engineered DG-TFET”, in Microsystem Technologies, Accepted (2020) (IF: 2.276)

90. Jaya Madan, Rahul Pandey & Rishu Chaujar, “Conducting Polymer Based Gas Sensor Using PNIN- Gate All Around - Tunnel FET”, Silicon, 12, pp.2947-2955, 2020. (IF: 2.67)
91. Shaveta Rajial, Maali Ahmed, Rishu Chaujar, “Rapid detection of biomolecules in a dielectric modulated GAN MOSHEMT”, Journal of Materials Science: Materials in Electronics, 31:16609–16615, 2020. (IF: 2.478)
92. Mridul P. Kashyap and Rishu Chaujar, “Gate Oxide Variability Analysis of a Novel 3nm Truncated Fin–FinFET for high circuitry Performance”, Vol. 13, pp. 3249–3256, Silicon Elsevier, 2021. (IF: 2.67)
93. Ajay Kumar, Neha Gupta and Rishu Chaujar, “Reliability of Sub-20 nm Black Phosphorus Trench (BP-T) MOSFET in High-Temperature Harsh Environment”, Silicon, Elsevier, 13, pp. 1277–1283(2021). (IF: 2.67)

94. Bhavya Kumar and Rishu Chaujar, “Analog and RF Performance Evaluation of Junctionless Accumulation Mode (JAM) Gate Stack Gate All Around (GS-GAA) FinFET”, Silicon, Elsevier, Vol.13, pp. 919–927, 2021. (IF: 2.67)

95. Samriti Sharma and Rishu Chaujar, “Band Gap and Gate Metal Engineering of Novel Hetero-material InAs/GaAs Based JLTFET for Improved Wireless Applications”, Journal of Materials Science: Materials in Electronics, Volume 32, pages: 3155–3166, 2021. (IF: 2.478)
96. Mridul P. Kashyap, Sanmveg Saini and Rishu Chaujar, “Analysis of a Novel Nanoscale Vacuum Channel TF-FinFET”, Vol. 13, pp. 3257–3269, Silicon, Elsevier (2021). (IF: 2.67)
97. Lakshya Gangwani, Ruchika Chakravarti, Rishu Chaujar, “Investigation of a Novel 5nm Top Bottom Gated Junctionless FinFET for Improved Switching and Analog Performance”, Journal of Physics: Conference Series 1921 (2021) 012100, doi:10.1088/1742-6596/1921/1/012100.
98. Bhavya Kumar and Rishu Chaujar, “TCAD Temperature Analysis of Gate Stack Gate All Around (GS-GAA) FinFET for Improved RF and Wireless Performance, Vol. 13, pp: 3741–3753 Silicon, Elsevier (2021). (IF: 2.67)
99. Samriti Sharma and Rishu Chaujar, “Performance enhancement in a novel amalgamation of arsenide/ antimonide tunneling interface with charge plasma junctionless-TFET”, AEU - International Journal of Electronics and Communications, Volume 133, May 2021, 153669. (IF: 3.183)
100. Vijayakumar Chinnadurai, Ardaman Kaur and Rishu Chaujar, “Assessment of distinct subcortical and cortical contributions to affect and approach/withdrawal behavior by means of resting-state functional connectivity approach”, Behavioral Neuroscience, Accepted, 2021. (IF: 1.912)
101.  Ajay Kumar, Uddeshya Gupta, Tanya, Rishu Chaujar, M.M.Tripathi and Neha Gupta, “Simulation of perovskite solar cell employing ZnO as electron transport layer (ETL) for improved efficiency”, Materials Today: Proceedings, Vol.46, pp.1684-1687, 2021
102.  Megha Sharma and Rishu Chaujar, “Design and Investigation of Recessed-T-Gate Double Channel HEMT with InGaN Back Barrier for Enhanced Performance Arabian Journal for Science and Engineering”, Arabian Journal for Science and Engineering, 47, 1109-1116, 2022. (IF: 2.334)
103. Megha Sharma and Rishu Chaujar, “Ultrascaled 10 nm T-gate E-mode InAlN/AlN HEMT with polarized doped buffer for high power microwave applications”, International Journal of RF and Microwave Computer&-Aided Engineering, Vol.32, Issue 4, April 2022.
104.  Bhavya Kumar and Rishu Chaujar, “Numerical Study of JAM-GS-GAA FinFET: a Fin Aspect Ratio Optimization for Upgraded Analog and Intermodulation Distortion Performance”, Silicon, 14, 309-321, 2022. (IF: 2.67)
105. Bhavya Kumar and Rishu Chaujar, “Numerical simulation of analog metrics and parasitic capacitances of GaAs GS-GAA FinFET for ULSI switching applications.”, European Physical Journal Plus, 137, Article No.110, 2022.
106. Samriti Sharma and Rishu Chaujar, “RF, linearity and intermodulation distortion analysis with small-signal parameters extraction of tunable bandgap arsenide/antimonide tunneling interfaced JLTFET”, Microsystem Technologies, 28, pages2659–2667 (2022) (2022)
107. Samriti Sharma and Rishu Chaujar, “Influence of Source Electrode Metal Work Function on Polar Gate Prompted Source Hole Plasma in Arsenide/Antimonide Tunneling Interfaced Junctionless TFET”, Journal of Micromechanics and Microengineering, Vol.32, No.4, 044004, 2022.
108. Samriti Sharma and Rishu Chaujar, “Impact of Tunnel Gate Process variations on Analog/RF (Microwave) and Small Signal Parameters of Hetero-material Tunneling Interfaced Charge Plasma Junctionless TFET", International Journal of Circuit Theory and Applications, Volume50, Issue10 October 2022, Pages 3626-3641 (2022)
109.  Mekonnen Getnet and Rishu Chaujar, “Sensitivity Analysis of Biomolecule Nano-Cavity Immobilization in Dielectric Modulated Triple Hybrid Metal Gate-All-Around Junctionless NWFET Biosensor for Detecting Various Diseases”, Journal of Electronic Materials, 51, pp. 2236–2247 (2022).
110. Mridul Prakash Kashyap, Harshal Gudaghe and Rishu Chaujar, “Compatibility of a Truncated Fin-FinFET as a k-modulated Biosensor with Optimum parameters for Pre-emptive Diagnosis of Diseases”, Computers and Electrical Engineering, Vol.100, 107850, May 2022
111.  Yash Pathak, B.D. Malhotra and Rishu Chaujar, “Detection of biomolecules in dielectric modulated double metal below ferroelectric layer FET with improved sensitivity”, Journal of Materials Science: Materials in Electronics, 33, pages13558–13567 (2022).
112. Rashi Mann and Rishu Chaujar, “TCAD investigation of Ferroelectric based substrate MOSFET for digital application”, 14, pages5075–5084 (2022) Silicon, Elsevier (2022). (IF: 2.67).
113.  Gaurav Mangal, Aman Tyagi and Rishu Chaujar, “Numerical Investigation of temperature based analog performance of fully gate covered Junctionless FinFET”, Computers and Electrical Engineering, Volume 101, July 2022, 108071.
114. Yash Pathak, B.D. Malhotra and Rishu Chaujar, “Analog/RF Performance and Effect of Temperature on Ferroelectric layer Improved FET device with Spacer” Silicon, 14, pages12269–12280 (2022)
115.  Tripti Gaur, Rahul Sharma and Rishu Chaujar, “Quantum ATK analysis of silicon nanowire FET with a cylindrical metallic wrap-around gate varied with dielectrics”, Materials Today Proceedings (2022)
116. Megha Sharma, Bhavya Kumar and Rishu Chaujar, “ Simulation investigation of double-heterostructure T-Gate HEMT with graded back barrier engineering for improved RF performance”, Materials Today Proceedings, 2022.
117.  Megha Sharma, Bhavya Kumar and Rishu Chaujar, “Polarization induced doping and high-k passivation engineering on T-gate MOS-HEMT for improved RF/microwave performance”, Materials Science and Engineering: B, Volume 290, April 2023, 116298.
118.  Rishu Chaujar & Mekonnen Getnet Yirak, “Sensitivity Investigation of Junctionless Gate-all-around Silicon Nanowire Field-Effect Transistor-Based Hydrogen Gas Sensor”, Silicon, Vol. 15, pages 609–621 (2023).
119. Yash Pathak, B.D. Malhotra and Rishu Chaujar, “DFT based atomic modeling and Analog/RF analysis of ferroelectric HfO2 based improved FET device”, Physica Scripta, Vol.98, No.8, 085933, 2023.
120.  Megha Sharma, Bhavya Kumar and Rishu Chaujar, “Small signal and noise analysis of T-gate HEMT with polarization doped buffer for LNAs”, Micro and Nano Structures, Vol.180, 207593, August 2023.
121. Bhavya Kumar, Megha Sharma and Rishu Chaujar “Gate electrode work function engineered JAM-GS-GAA FinFET for analog/RF applications: Performance estimation and optimization”, Microelectronics journal, Vol.135, 105766, May 2023.
122. B. Kumar, M. Sharma, and R. Chaujar, “Junctionless-accumulation-mode stacked gate GAA FinFET with dual-k spacer for reliable RFIC design,” Microelectronics Journal, vol. 139, 105910, 2023.
123. B. Kumar and R. Chaujar, “Fin field-effect-transistor engineered sensor for detection of MDA-MB-231 breast cancer cells: A switching-ratio-based sensitivity analysis,” Physical Review E, vol. 108, 034408, 2023. (IF – 2.4)
124. Rashi Mann and Rishu Chaujar, “DFT-based Atomic Calculation of Si-doped HfO2 and Effect of its Negative Capacitance on Analog/RF, and VTC Parameters of MOSFET”, Silicon, Vol.16, pp.1237-1252, 2024.
125. R. Mann, R. Chaujar, “DFT-based Atomic Modeling and Temperature Analysis on the RF and VTC curve of high-k dielectric layer-assisted NCFET,” Physica Scripta, 99(1), 015029, (2024).
126. Yash Pathak, Piyush Mishra, Megha Sharma, Shipra Solanki, Ved Varun Agarwal, Rishu Chaujar, Bansi Dhar Malhotra, “Experimental circuit design and TCAD analysis of ion sensitive field effect transistor (ISFET) for pH sensing”, Materials Science and Engineering: B, Volume 299, January 2024, 116951.
127. Mekonnen Getnet and Rishu Chaujar, ‘Investigation of Gate-Stack Gate-All-Around Junctionless Nanowire Field Effect Transistor for Oxygen Gas Sensing", Journal of Electronic Materials, volume 53, issue 4, pages 2191-2201,  (2024).
128. Megha Sharma and Rishu Chaujar, “Device Optimization of T-shaped gate and polarized doped buffer engineered InAlN/GaN HEMT for improved RF/ microwave performance’, Arabian Journal for Science and Engineering, Issue 7, (2024).
129. Samriti Sharma, Jaya Madan and Rishu Chaujar, “Interfacial Charge Associated Reliability Improvement in Arsenide/Antimonide Tunneling Interfaced-Junctionless TFET”, Physics Scripta Vol.99,No.4, 2024
130. R. Mann, R. Chaujar, “Self-Consistent LCAO based DFT analysis of high-k spacers and its assessment on Gate-Stacked NCFET for improved device-circuit performance,” Silicon, pp.5185-5197, Vol.16, 2024.
131. Anshul and Rishu Chaujar, “Semi Empirical DFT based investigation of Electronic and quantum transport properties of Novel GS-AGNR (N) FET”, IEEE TNANO, Vol.23, pp.400-407, 2024.
132. Mekonnen Getnet and Rishu Chaujar, “Effect of trap charges on Dielectric Modulated Triple Hybrid Metal Gate Junctionless Gate All Around Silicon Nanowire FET based APTES & Biotin Biosensor”, Silicon Journal (Springer), (Submitted), 2023.  
133. Kajal Verma and Rishu Chaujar, “Optimization and analysis of Si/SiGe strained vertically stacked heterostructure on insulator FeFinFET for high performance analog and RF applications”, Physica Scripta, 99 115960, 2024.
134. Samriti Sharma, Jaya Madan and Rishu Chaujar, “Exploring tunable arsenide/antimonide tunneling interfaced junctionless TFET for gas sensing applications”, Material Science and Engineering: B, Volume 305, July 2024, 117450
135. K. Verma and R. Chaujar, "Unveiling the Impact of Interfacial Trap Charges on Strained VS-FeFinFETs for Improved Reliability:Device to Circuit Level Assessment," in IEEE Transactions on Nanotechnology, vol. 24, pp. 88-95, 2025
136. Yash Pathak, Kajal Verma, Bansi Dhar Malhotra and Rishu Chaujar,"Performance Evaluation of Gate Engineered Ferroelectric MIMOS for Analog/Electrical IC Applications", Physica Scripta, 100 015028, 2025.
137. Mekonnen Getnet and Rishu Chaujar, “Numerical Modelling for triple hybrid gate optimization dielectric modulated junctionless gate all around SiNWFET based uricase and ChOX biosensor,” Vol.31, pp.103-122, Microsystem Technologies, 2025. 
138.  S. Sharma, J. Madan and R. Chaujar, "Insights Into Temperature Sensitivity Analysis of Polarity Controlled Charge Plasma Based Tunable Arsenide/Antimonide Tunneling Interfaced Junctionless TFET," in IEEE Transactions on Nanotechnology, vol. 24, pp. 96-101, 2025
139. Shaveta, R. K. Bhan, Rishu Chaujar, “Design Optimization of MEMS Gyroscope for Enhanced Sensitivity, Bandwidth and Noise Reduction” communicated in Micro and Nano Structures.
140. Shaveta, R. K. Bhan, Rishu Chaujar, “Mitigating Thermal Effects in MEMS Gyroscopes: A Novel Substrate Integration Approach” communicated in Sensors and Actuators: A. Physical.
141. Mekonnen Getnet and Rishu Chaujar, “Comparative Assessment of Trap Charges Effect on Triple Hybrid Metal Gate Dielectric Modulated Junctionless Gate All Around Nanowire FET-Based Biosensor”, Advances in Condensed Matter Physics, 2025.
142.  Kajal Verma and Rishu Chaujar, “Reliability Analysis of the Intricacies of Interfacial Trap Charges in HD-VS-FeFinFET and its Applicability as CMOS Inverter”, Microelectronics Reliability, Volume 166, March, 11561

143.  Saood Ahmad, Jyoti Shah, Anurag K Katiyar, Rishu Chaujar, Nitin K Puri, PS Negi and RK Kotnala, “Microwave device jig characterization for ferromagnetic resonance induced spin Hall effect measurement in bilayer thin films”, Indian Journal of Pure and Applied Physics, Vol.54, pp.60-65, January 2016. (IF: 923)

144. Manju Singh, Rishu Chaujar, Sudhir Husale, S. Grover, Amit P. Shah, Mandar M. Deshmukh,  Anurag Gupta,  V. N. Singh,  V. N. Ojha,  D. K. Aswal,  R. K. Rakshit, “Influence of Fabrication Processes on Transport Properties of Superconducting Niobium Nitride Nanowires”, Current Science, Pages: 1443-1450, Vol 114, No 07 (2018)