Neeta Pandey

Electronics and Communication Engineering

Phone:0
Email: neetapandey@dce.ac.in

Qualifications

M. E. (Microelectronics) Ph. D.

Areas of Interest

Analog and Digital VLSI Design, Current mode ADC Design

Neeta Pandey

 

Electronics and Communication Engineering

 

Email: neetapandey@dce.ac.in

 

Qualifications :

 

M. E. (Microelectronics) Ph. D.

 

Areas of Interest

Analog and Digital VLSI Design, Current mode ADC Design

 

Summary

Motivated Teaching Professional with approximately 31 years teaching and research experience in Electronics and Communication Engineering. Accomplished lecturer who effectively articulates information and responds honestly to questions from students.

 

Highlights

 

  • Inspiring teacher with Effective Communication
  • Uphold high morale and ethics of this noble profession

 

Subjects Taught

 

  • VLSI Design
  • Deep Submicron VLSI Design
  • Basic and Advanced courses in Digital Electronics
  • Computer Architecture
  • Analog Filter design
  • Analog Integrated Circuits
  • Analog Electronics

 

Honours, awards and recognitions acquired by faculty

 

  • Member Editorial Board - AEU Int. J. Electronics and Communication, Advances in Electrical and Electronics Engineering
  • Excellence in research Award from Delhi Technological University Delhi for research papers published in SCI Journal Papers
  • Outstanding Branch Counsellor award from IEEE USA 2008 and cash prize of US $500.
  • Outstanding Branch Counsellor award from IEEE Delhi Section 2008.
  • Inclusion in Marquis Who’s who 2010
  • National Scholarship for class 10
  • Designated reviewer for International Journals published by Weily, IEEE, IET, Taylor and Francis, Springer and Elsevier.
  • Technical Program Chair for IEEE conference on Signal Processing, VLSI and Communication Engineering, 2019
  • Designated reviewer for International Conferences
  • Member of Technical Program Committee of International Conferences
  • Member of professional societies such as IEEE, Women in Engineering (WIE), an affinity group of IEEE, ISTE.
  • Technical Program Chair for IEEE conference on Signal Processing, VLSI and Communication Engineering

Accomplishment

  • Co-authored books
    • Model and Design of Improved Current Mode Logic Gates, Springer 2020
    • IC Analog Filter, LAP Lambert Academic Publishing, 2011, ISBN 978-3-8433-6007-4
    • Wave Filter: A Wave Active Equivalence Design Approach LAP Lambert Academic Publishing, 2011, ISBN 978-3844381696, 2011
    • Realization of analog controllers using OTRA, LAP Lambert Academic Publisher, West Germany, 2012, ISBN no. 978-3-659-16439-2
    • Dynamic Current Mode Logic: Concepts to Advancements, LAP LAMBERT Academic Publishing, 2021, ISBN-13: 978-620-4-20810-7
  • Co-authored book chapter

 

  • Awards/ Recognition
  • Outstanding Branch counsellor award from IEEE USA 2008 and cash prize of US $500.
  • Outstanding Branch Counsellor award from IEEE Delhi Section 2008
  • Inclusion in Marquis Who’s who 2010
  • Participated in IUCEE, Project GENTLE (Global Education Network for Teaching and Learning Engineering), in collaboration with Inpods Oct.2014. Received a letter of appreciation and cash prize.
  • Best paper Award for “OTRA based shadow filters” in IEEE India Conference (INDICON), Dec 2015.
  • Commendable Research Excellence Award in 2018,2019, 2020, 2021,2022,2023.
  • Citation Award 2022,2023.
  • Listed in 2% scientist by Stanford.

 

  • Memberships
    • Member of professional societies such as IEEE (Senior Member), Women in Engineering (WIE), an affinity group of IEEE, ISTE.

 

  • Institutional Governance responsibilities 
  • Director IQAC from Aug 2023
  • Coordinator TEQIP III project
  • Member Board of Studies ECE
  • Member Departmental research Committee, ECE and SE Departments
  • Member Departmental purchase Committee
  • ISO Internal Auditor
  • Coordinator University Student Internship Program

Patents Awarded: 3


 

Publications:

Journal Paper

 

Published

 

 

 

  1. L. Soni and N. Pandey, “A robust , low power and high speed radiation hardened 12T SRAM cell for space applications,” Microelectronics J., vol. 156, no. December 2024, p. 106502, 2025, doi: 10.1016/j.mejo.2024.106502. (SCIE Journal, IF: 1.9)
  2. K. Suneja, N. Pandey, and R. Pandey "Novel four dimensional hyperchaotic system: analysis, adaptive control, analog and digital circuit design." International Journal of Information Technology (2024): 1-9. (SCIE Journal, IF: 4.8)
  3. P. Gupta, N. Pandey, and R. Pandey. "Resistorless Realization of Three Port Circulator using Operational Transconductance Amplifiers." Journal of Circuits, Systems and Computers (2024). (SCIE Journal, IF: 0.9)
  4. S. Rewari, and N. Pandey. "Numerical simulation of core shell dual metal gate stack junctionless accumulation mode nanowire FET (CS-DM-GS-JAMNWFET) for low power digital applications." Micro and Nanostructures 196 (2024): 207995. (SCIE Journal, IF: 3.1)
  5. A. Pathak, M. K. Tiwari, N. Pandey, S. K. Paul, and S. M. I. Rizvi, “Programmable PVT compensated dual output resistance tunable current controlled conveyor,” Int. J. Electron., vol. 111, no. 12, pp. 2180–2198, 2023, doi: 10.1080/00207217.2023.2267209. (SCIE Journal, IF: 1.3)
  6. A. Mann, N. Pandey, and M. Gupta, “Novel high speed low power comparators imbibing Self-cascode preamplifier technique,” AEU - Int. J. Electron. Commun., vol. 185, no. July, 2024, doi: 10.1016/j.aeue.2024.155429. (SCIE Journal, IF: 3)
  7. A. Pathak, M. K. Tiwari, N. Pandey, S. K. Paul, and S. M. I. Rizvi, “Programmable PVT compensated dual output resistance tunable current controlled conveyor,” Int. J. Electron., vol. 111, no. 12, pp. 2180–2198, 2023, doi: 10.1080/00207217.2023.2267209. (SCIE Journal, IF: 1.3)
  8. N. Kumar, M. Kumar, and N. Pandey, “Grounded and floating memristor emulator employing ICCTA: decremental or incremental operation,” Int. J. Electron., vol. 00, no. 00, pp. 1–22, 2024, doi: 10.1080/00207217.2024.2372063. (SCIE Journal, IF: 1.3)
  9. S. Gupta, N. Pandey, and R. S. Gupta, “Small Signal Parameters Extraction and RF Performance of GaN-Based Dual-Metal Cylindrical Surrounding Gate Junctionless Accumulation-Mode (DM-CSG-JAM) MOSFET,” IETE J. Res., vol. 70, no. 10, pp. 7969–7979, 2024, doi: 10.1080/03772063.2024.2358148. (SCIE Journal, IF: 1.3)
  10. L. Soni and N. Pandey, “A low power Schmitt-trigger driven 10T SRAM Cell for high speed applications,” Integration, vol. 97, no. February, p. 102187, 2024, doi: 10.1016/j.vlsi.2024.102187. (SCIE Journal, IF: 2.2)
  11. O. K. Gupta, N. Pandey, and M. Gupta, “Improved frequency compensation technique of three stage amplifier using class AB flipped voltage follower and slew rate enhancer circuit,” AEU - Int. J. Electron. Commun., vol. 177, no. February, p. 155173, 2024, doi: 10.1016/j.aeue.2024.155173. (SCIE Journal, IF: 3)
  12. S. Gupta, N. Pandey, and R. S. Gupta, “Non-uniform doping dependent electrical parameters of dual-metal gate all around junctionless accumulation-mode nanowire FET (DMGAA-JAM-NWFET),” Int. J. Numer. Model. Electron. Networks, Devices Fields, vol. 37, no. 2, pp. 1–17, 2024, doi: 10.1002/jnm.3203. (SCIE Journal, IF: 1.6)
  13. L. Soni and N. Pandey, “A Reliable and high performance Radiation Hardened Schmitt Trigger 12T SRAM cell for space applications,” AEUE - Int. J. Electron. Commun., vol. 176, no. February, p. 155161, 2024, doi: 10.1016/j.aeue.2024.155161. (SCIE Journal, IF: 3)
  14. A. K. Trivedi, S. Garg, and N. Pandey, “Novel hardware/software co-design approach for Connect6 game-solver,” e-Prime - Adv. Electr. Eng. Electron. Energy, vol. 7, no. December 2023, p. 100395, 2024, doi: 10.1016/j.prime.2023.100395. (SCIE Journal, IF: 2.1)
  15. L. Soni and N. Pandey, “A Single Bitline Highly Stable, Low Power With High Speed Half-Select Disturb Free 11T SRAM Cell,” ACM Trans. Des. Autom. Electron. Syst., vol. 29, no. 4, pp. 1–13, 2024, doi: 10.1145/3653675. (SCIE Journal, IF: 2.2)
  16. S. Gupta, N. Pandey, and R. S. Gupta, “Analytical model for junctionless accumulation-mode cylindrical surrounding gate (JAM-CSG) MOSFET as a biosensor,” Int. J. Numer. Model. Electron. Networks, Devices Fields, vol. 36, no. 5, p. e3095, 2023, doi: https://doi.org/10.1002/jnm.3095. (SCIE Journal, IF: 1.6)
  17. N. Kumar, M. Kumar, and N. Pandey, “Electronically tunable positive and negative fractional order inductor circuit using single topology,” Integration, vol. 88, pp. 379–389, 2023, doi: https://doi.org/10.1016/j.vlsi.2022.10.007. (SCIE Journal, IF: 1.9)
  18. N. Kumar, M. Kumar, and N. Pandey, “CCTA based four different pairs of mutually coupled circuit using single topology,” Integration, vol. 91, pp. 43–53, 2023, doi: https://doi.org/10.1016/j.vlsi.2023.02.009. (SCIE Journal, IF: 1.9)
  19. N. Kumar, M. Kumar, and N. Pandey, “A programmable tunable active grounded and floating immittance circuit using CCTA and their applications,” Int. J. Electron., vol. 110, no. 1, pp. 73–106, 2023, doi: 10.1080/00207217.2021.2001876. (SCIE Journal, IF: 1.3)
  20. A. Pathak, M. K. Tiwari, N. Pandey, S. K. Paul, and S. M. I. Rizvi, “Reliability Analysis of Radiation Tolerant Low Voltage CCCII Circuit For Space Applications,” Def. Sci. J., vol. 72, no. 6, pp. 854–863, 2022, doi: 10.14429/dsj.72.17583. (SCIE Journal, IF: 0.67)
  21. D. Singh, K. Gupta, and N. Pandey, “A novel read decoupled 8T1M nvSRAM cell for near threshold operation,” Microelectronics J., vol. 126, p. 105496, 2022, doi: https://doi.org/10.1016/j.mejo.2022.105496. (SCIE Journal, IF: 2.2)
  22. D. Singh, N. Pandey, and K. Gupta, “Process invariant Schmitt Trigger non-volatile 13T1M SRAM cell,” Microelectronics J., vol. 135, p. 105773, 2023, doi: https://doi.org/10.1016/j.mejo.2023.105773. (SCIE Journal, IF: 2.2)
  23. D. Singh, N. Pandey, and K. Gupta, “Schmitt Trigger 12T1M Non-volatile SRAM cell with improved process variation tolerance,” AEU - Int. J. Electron. Commun., vol. 162, p. 154573, 2023, doi: https://doi.org/10.1016/j.aeue.2023.154573. (SCIE Journal, IF: 3.2)
  24. D. Singh, N. Pandey, and K. Gupta, “A novel read decoupled 8T1M nvSRAM cell with improved read/write margin,” Analog Integr. Circuits Signal Process., vol. 114, no. 1, pp. 89–101, 2023, doi: 10.1007/s10470-022-02121-z. (SCIE Journal, IF: 1.4)
  25. L. Soni and N. Pandey, “A novel CNTFET based Schmitt-Trigger read decoupled 12T SRAM cell with high speed, low power, and high Ion/Ioff ratio,” AEU - Int. J. Electron. Commun., vol. 167, p. 154669, 2023, doi: https://doi.org/10.1016/j.aeue.2023.154669. (SCIE Journal, IF: 3.2)
  26. K. Suneja, N. Pandey, and R. Pandey, “A Novel Chaotic System with Exponential Nonlinearity and its Adaptive Self-Synchronization: From Numerical Simulations to Circuit Implementation,” J. Circuits, Syst. Comput., vol. 32, no. 17, p. 2350296, 2023, doi: 10.1142/S0218126623502961. (SCIE Journal, IF: 1.5)
  27. Shikha, N. Pandey, and K. Gupta, “Memristor-Based Architectures for PFSCL Circuit Realizations,” Circuits, Syst. Signal Process., vol. 42, no. 8, pp. 4985–5012, 2023, doi: 10.1007/s00034-023-02346-x. (SCIE Journal, IF: 2.3)
  28. K. Suneja, N. Pandey, and R. Pandey, “Systematic Realization of CFOA Based Rössler Chaotic System and Its Applications,” Arab. J. Sci. Eng., vol. 47, no. 11, pp. 13799–13810, 2022, doi: 10.1007/s13369-021-06379-9. (SCIE Journal, IF: 2.9)
  29. I. Tomar, I. Sreedevi, and N. Pandey, “PLC and SCADA based Real Time Monitoring and Train Control System for the Metro Railways Infrastructure,” Wirel. Pers. Commun., vol. 129, no. 1, pp. 521–548, 2023, doi: 10.1007/s11277-022-10109-1. (SCIE Journal, IF: 2.2)
  30. G. Varshney, N. Pandey, and S. Minaei, “CIM applications in fractional domain: Fractional-order universal filter & fractional-order oscillator,” AEU - Int. J. Electron. Commun., vol. 156, p. 154408, 2022, doi: https://doi.org/10.1016/j.aeue.2022.154408. (SCIE Journal, IF: 3.2)
  31. G. Varshney, N. Pandey, and R. Pandey, “Design and implementation of OTA based fractional-order oscillator,” Analog Integr. Circuits Signal Process., vol. 113, no. 1, pp. 93–103, 2022, doi: 10.1007/s10470-022-02069-0. (SCIE Journal, IF: 1.4)
  32. N. Yadav, N. Pandey, and D. Nand, “LDML: A Proposal to Reduce Leakage Power in DML Circuits,” Wirel. Pers. Commun., vol. 129, no. 2, pp. 1009–1024, 2023, doi: 10.1007/s11277-023-10170-4. (SCIE Journal, IF: 2.2)
  33. N. Yadav, N. Pandey, and D. Nand, “Modified Dual Mode Transmission Gate Diffusion Input Logic for Improving Energy Efficiency,” J. Circuits, Syst. Comput., vol. 32, no. 10, p. 2350171, 2023, doi: 10.1142/S0218126623501712. (SCIE Journal, IF: 1.5)
  34. D Singh, K. Gupta, N. Pandey, A Novel Low-Power Nonvolatile 8T1M SRAM Cell, Arabian Journal for Science and Engineering, 47, 3163-3179,2022 (SCI – 2.334)
  35. R. Sivaram, K. Gupta, N. Pandey, On improving the performance of dynamic positive-feedback source-coupled logic (D-PFSCL) through inclusion of transmission gates, Microprocessors and Microsystems, 90, 104521, 2022. (SCI – 1.525)
  36. S. Singh, S. Jain, R. Pandey, N. Pandey Adaptive biased current differencing trans-conductance amplifier, AEU - International Journal of Electronics and Communications, 128, 153494, Jan 2021. (SCI – 3.183)
  37. M. Gupta, K. Gupta, N. Pandey A data?independent 9T SRAM cell with enhanced ION/IOFF ratio and RBL voltage swing in near threshold and sub?threshold region, International Journal of Circuit Theory and Applications, 49, 4, Apr 2021, 953-969. (SCI – 2.038)
  38. M. Gupta, K. Gupta, N. Pandey, Comparative Analysis of the Design Techniques for Low Leakage SRAMs at 32nm, Microprocessors and Microsystems, 85, 2021. (SCI – 1.525)
  39. M. Gupta, K. Gupta,N. Pandey, A novel PVT-variation-tolerant Schmitt-trigger-based 12T SRAM cell with improved write ability and high ION/IOFF ratio in sub-threshold region, International Journal of Circuit Theory and Applications, 49, 11, November 2021. Pages 3789-3810 (SCI – 2.038)
  40. S Gupta, N. Pandey, RS Gupta, Analytical modeling of dual-metal gate stack engineered junctionless accumulation-mode cylindrical surrounding gate (DMGSE-JAM-CSG) MOSFET, Appl. Phys. A, 127, 2021, 520. (SCI – 2.584)
  41. S. Gupta, N. Pandey, RS Gupta, Temperature dependency and linearity assessment of dual-metal gate stack junctionless accumulation-mode cylindrical surrounding gate (DMGS-JAM-CSG) MOSFET, Physica Scripta 96 (12), 124055 (SCI – 2.487)
  42. N. Kumar, M. Kumar, N. Pandey, Unified floating immittance emulator based on CCTA, Microelectronics Journal 118, 105289, 2021 (SCI – 1.605)
  43. R. Arundeepakvel, Jatin, P. Khatter, N. Pandey, Shahram Minaei, A novel design for voltage inverting metamutator and its applications, Microelectronics Journal, 113, 2021. (SCI – 1.605)
  44. N. Yadav, N. Pandey, D. Nand, Leakage reduction in dual mode logic through gated leakage transistors, Microprocessors and Microsystems, 84, 2021. (SCI – 1.525)
  45. A. S. Kumar, S. Jain, N. Pandey, Clock Aligned Input Adiabatic Logic, Microelectronics Journal, 114, 105122, 2021. (SCI – 1.605)
  46. R. Sivaram, K. Gupta & N. Pandey, Impact of multi threshold transistor in positive feedback source coupled logic (PFSCL) fundamental cell, Analog Integrated Circuits and Signal Processing, 109, 173- 185, 2021. (SCI – 1.337)
  47. G. Varshney, N. Pandey, R. Pandey, Electronically Tunable Multifunction Transadmittance-Mode Fractional-Order Filter, Arabian Journal for Science and Engineering, 46, 1067–1078, 2021. (SCI – 2.334)
  48. G .Varshney, N. Pandey, R. Pandey, Electronically tunable fractional-order multivibrator using OTA and its application as versatile modulator, AEU-International Journal of Electronics and Communications 141, 153956, 2021 (SCI – 3.183)
  49. G. Varshney, N. Pandey, R. Pandey, Generalization of shadow filters in fractional domain, International Journal of Circuit Theory and Applications, 49, 10, October 2021,Pages 3248-3265 (SCI – 2.038)
  50. P. Kumar, N. Pandey, SK Paul, Electronically Tunable VDTA-Based Multi-function Inverse Filter, Iranian Journal of Science and Technology, Mar 2021. (SCI – 1.194)
  51. O. K. Gupta, N. Pandey M. Gupta, Improved reversed nested miller frequency compensation techniques using flipped and folded flipped voltage follower with resistor for three stage amplifier AEU - International Journal of Electronics and Communications, 142, 154004, 2021. (SCI – 3.183)
  52. C. Parashar, A. Kumar Trivedi, A. Agarwal, N. Pandey, Footer Voltage Controlled Dual Keeper Domino Logic with Static Switching Approach, Advances in Electrical and Electronic Engineering, 18, 4, 255- 263, 2020. Scopus
  53. R. Jain, K. Gupta, N. Pandey, Hybrid Dynamic CML with Modified Current Source (H-MDyCML): A Low-Power Dynamic MCML Style, Advances in Electrical and Electronic Engineering, 19, 1, 57-65, 2021. Scopus
  54. R Jain, K Pahwa, N. Pandey, Booth-Encoded Karatsuba: A Novel Hardware-Efficient Multiplier, Advances in Electrical and Electronic Engineering 19 (3), 272-281, 2021. Scopus
  55. M. Bhardwaj, S. Pandey, N. Pandey, A Novel Design of High-Performance Low Power Phase-Frequency Detector for CMOS PLL Frequency Synthesizer, International Journal of Sensors Wireless Communications and Control, 10, 6, 2020, 838-845. Scopus
  56. S Singh, Jatin, N. Pandey, R. Pandey, Electronically Tunable Grounded Capacitance Multiplier, IETE Journal of Research, 1-12, 2020 (SCI - 2.333)
  57. N. Pandey, R. Pandey, R Anurag, R Vijay, A Class of Differentiator-Based Multifunction Biquad Filters Using OTRAs, Advances in Electrical and Electronic Engineering 18 (1), 31-40, 2020 Scopus
  58. P Sharma, S Gupta, K. Gupta, N. Pandey, A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability, Microelectronics J., 97, 104703, 2020 (SCI – 1.605)
  59. G. Komanapalli, R. Pandey, N. Pandey New Electronically tunable low-frequency quadrature oscillator using operational transresistance amplifier, IETE Journal of Research, 1-9, 2020 (SCI - 2.333)
  60. S Jain, N. Pandey, Single Clock Diode Based Adiabatic Logic Family at Sub-90nm Regime, Advances in Electronics Engineering, 245-259, 2020
  61. R. Jain, N. Pandey, Realization of Various Topologies of Adders Based on H-DyCML, International Journal of Innovative Technology and Exploring Engineering (IJITEE), 9, 1885-1191 2020
  62. V. Bhanoo, A. Gangal, N.Pandey, Subthreshold Low-Transconductance M-CDTA based Low Frequency Current Mode Universal Filter, International Journal of Engineering Trends and Technology, 68(5), 16- 22, 2020
  63. R. Singh, N. Pandey, A Low Power and Area Efficient Design of Dadda Multiplier by exploring 4:2 Compressors and Brent Kung Adder, International Journal of Advanced Science and Technology, 29, 10044-10054, 2020.
  64. P. Kumar, N. Pandey, S. K. Paul, Realization of Resistorless and Electronically Tunable Inverse Filters Using VDTA, Journal of Circuits, Systems and Computers 28 (09), 1950143, 2019
  65. G. Komanapalli, R. Pandey, N. Pandey, Operational Transresistance Amplifier Based Wienbridge Oscillator and Its Harmonic Analysis, Wireless Personal Communications 108 (1), 1-17, 2019
  66. E. Yuce, R. Verma, N. Pandey, S. Minaei, New CFOA-based first-order all-pass flters and their applications. AEU - International Journal of Electronics and Communications, 103, 57-63, 2019. (SCI – 3.183)
  67. S. Gupta, K. Gupta, B. H. Calhoun, N. Pandey, Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS. IEEE Transactions on Circuits and Systems I: Regular Papers, 66(3), 978–988, 2019. (SCI-3.605)
  68. M. Gupta, K. Gupta, N. Pandey. A design of low leakage cache memory cell for high performance processors. Journal of Information and Optimization Sciences 40 (2), 279-290, 2019
  69. R. Verma, N. Pandey, R. Pandey. CFOA based low pass and high pass fractional step filter realizations. AEU-International Journal of Electronics and Communications 99, 161-176, 2019 (SCI – 3.183)
  70. P Bajpai, N. Pandey, K. Gupta, J Panda, LECTOR incorporated differential cascode voltage swing logic (L-DCVSL), Analog Integrated Circuit and Signal Processing 100 (1), 221-234, 2019 (SCI – 1.337)
  71. M. Tiwari, N. Pandey, SK Paul, M. Rizvi. Programmable CCCII: Reliability Analysis and Design Methodology. IET Circuits, Devices & Systems, 13, 4, 487-493, July 2019. (SCI – 1.297)
  72. G. Komanapalli, R. Pandey, N. Pandey. New sinusoidal oscillator configurations using operational transresistance amplifier. International Journal of Circuit Theory and Applications, 47, 5 Pages 666- 685 May 2019 (SCI – 2.038)
  73. A Mann, N Malhotra, N. Pandey Adaption of Power Gating in Positive Feedback Adiabatic Logic Circuits, International Journal of Advance Research and Innovation, 7 (3), 281-284, 2019
  74. A Jain, N. Pandey, P Jain. FPGA-Based Architecture for Implementation of Discrete Sine Transform. Advances in System Optimization and Control, 13-22, 2019
  75. P. Pahalwan, P. Tripathi, P. Gola, N. Pandey, D Nand, Programmable Gain Amplifier Using Operational Floating Current Conveyors, AEU-International Journal of Electronics and Communications, 90, 163- 170, 2018. (SCI – 3.183)
  76. S. Gupta, K. Gupta, N. Pandey, Pentavariate Vmin Analysis of a Subthreshold 10T SRAM Bit Cell With Variation Tolerant Write and Divided Bit-Line Read IEEE Transactions on Circuits and Systems I: 65, 10, 3326 – 3337,2018. (SCI-3.605)
  77. V. Bhatnagar, P. Kumar, N. Pandey, S Pandey, A dual V t disturb-free subthreshold SRAM with write- assist and read isolation, Journal of Semiconductors 39 (2), 025002, 2018. Scopus
  78. V. Bhatnagar, P. Kumar, N. Pandey, S Pandey, A boosted negative bit-line SRAM with write-assisted cell in 45 nm CMOS technology Journal of Semiconductors 39 (2), 025001, 2018 Scopus
  79. S. Oruganti, N. Pandey, R. Pandey, Electronically tunable high gain current-mode instrumentation amplifier, AEU-International Journal of Electronics and Communications 95, 16-23, 2018 (SCI – 3.183)
  80. R Verma, N. Pandey, R. Pandey, Realization of a higher fractional order element based on novel OTA based IIMC and its application in filter, Analog Integrated Circuits and Signal Processing, 97 (1), 177- 191, 2018. (SCI – 1.337)
  81. G. Komanapalli, N. Pandey, R. Pandey, New realization of third order sinusoidal oscillator using single OTRA, AEU-International Journal of Electronics and Communications 93, 182-190, 2018 (SCI – 3.183)
  82. S. Oruganti, Y Gilhotra, N. Pandey, R. Pandey, OTRA Based Piece-Wise Linear VTC Generators and Their Application in High-Frequency Sinusoid Generation, Advances in Electrical and Electronic Engineering 15 (5), 806-814, 2018 Scopus
  83. D Nand, N. Pandey, New Configuration for OFCC-Based CM SIMO Filter and its Application as Shadow Filter, Arabian Journal for Science and Engineering, 1-12, 2018 (SCI-2.334)
  84. N. Pandey, B. Choudhary, K. Gupta, A Mittal, New Sleep-Based PFSCL Tri-State Inverter/Buffer Topologies, Journal of Circuits, Systems and Computers, 1750186, 2017
  85. R. Verma, N. Pandey, R. Pandey, Electronically Tunable Fractional Order Filter, Arabian Journal for Science and Engineering, 1-14, 2017 (SCI-2.334)
  86. N. Pandey, V. Kumar, A. Goel, A. Gupta, Electronically tunable LC high pass ladder filter using OTRA, 10.21917/ijme.2017.0079, 2017
  87. S. Gupta, K. Gupta, N. Pandey, A 32-nm Subthreshold 7T SRAM Bit Cell With Read Assist, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25 12,  3473-3483, 2017 (SCI-2.312)
  88. L. Safari, N. Pandey, N Herencsar, F Khateb, Special Issue on Current-Mode Circuits and Systems; Recent Advances, Design and Applications, AEU-International Journal of Electronics and Communications, 2017 (SCI – 3.183)
  89. K. Gupta, N. Pandey, M. Gupta, Dynamic positive feedback source-coupled logic (D-PFSCL) International Journal of Electronics 103 (10), 1626-1638, 2016 (SCI – 1.336)
  90. N. Pandey, K. Gupta, B. Choudhary, New Proposal for MCML Based Three-Input Logic Implementation, VLSI Design 2016 Article ID 8712768
  91. P. Bajpai, N. Pandey, K. Gupta, S Bagga, J Panda, On Improving the Performance of Dynamic DCVSL Circuits, Journal of Electrical and Computer Engineering 2017 Article ID 8207104
  92. V. Bhatia, N. Pandey, Modified Tang and Pun’s Current Comparator and Its Application to Full Flash and Two-Step Flash Current Mode ADCs, Journal of Electrical and Computer Engineering 2017 Article ID 8245181
  93. G. Komanaplli, N. Pandey, R. Pandey New Realization of Quadrature Oscillator using OTRA International Journal of Electrical and Computer Engineering (IJECE) vol. 7, No. 1815-1823 Aug 2017
  94. R. Verma, N. Pandey, R. Pandey, Electronically Tunable Fractional Order All Pass Filter, IOP Conference Series: Materials Science and Engineering 225 (1), 012229, 2017
  95. P. Gupta, R. Pandey, N. Pandey, Voltage Mode Single CDBA Based Multifunction Filter IOP Conference Series: Materials Science and Engineering 225 (1), 012243, 2017
  96. G. Komanapalli, N. Pandey, R. Pandey, Single OTRA Based Low Frequency Sinusoidal Oscillator Realization, IOP Conference Series: Materials Science and Engineeri 225 (1), 012151, 2017
  97. D. Nand, N. Pandey, Transadmittance Mode First Order LP/HP/AP Filter and its Application as an Oscillator, IOP Conference Series: Materials Science and Engineering 225 (1), 012150, 2017
  98. D. Nand, N. Pandey, A New Proposal for OFCC-based Instrumentation Amplifier, International Journal of Electrical and Computer Engineering 7 (1), 134, 2017
  99. N. Pandey, G Varshney, R. Pandey, Differential Voltage Current Conveyor Realization based on CMOS Inverters, i-Manager's Journal on Electronics Engineering 7 (2), 14,2016
  100. N. Pandey, R. Pandey, N. Sabharwal, Realization of Diode-Free OTRA based Time Marker Generator, i-Manager's Journal on Electronics Engineering 7 (1), 16, 2016
  101. K. Gupta, P Gupta, R. Pandey, N. Pandey CDBA -Current Based Instrumentation Amplifier, Journal of Communications Technology, Electronic s and Computer Science, 4, 2016
  102. Nitish, N. Pandey, K. Gupta, M K Saini, DFAL based flexible multi-modulo prescaler, ICTACT Journal on Microelectronics,  273-280, 2016
  103. N. Saxena, S Dutta, N. Pandey, An Efficient Hybrid PFSCL based Implementation of Asynchronous Pipeline, i-Manager's Journal on Circuits & Systems 4 (3), 6 - 14, 2016
  104. N. Pandey, K. Gupta, G Bhatia, B. Choudhary, MOS Current Mode Logic Exclusive-OR Gate using Multi-Threshold Triple-Tail Cells, Microelectronics Journal. 57,  13–20, 2016 (SCI – 1.605)
  105. N. Pandey, K. Gupta, B. Choudhary, New proposal for MCML based three input logic implementation, VLSI Design, 2016, Article ID 8712768, 10 pages
  106. R. Pandey, N. Pandey, N Singhal, Single VDTA Based Dual Mode Single Input Multi output Biquad Filter, Journal of Engineering, 2016, Article ID 1674343, 10 pages,
  107. D. Nand, N. Pandey, A new proposal for OFCC based Instrumentation Amplifier, International Journal of Electrical and Computer Engineering, 7, 1,31 – 39, 2016. (SCIE-4.360)
  108. S. Kumari, S Gupta, N. Pandey, R. Pandey, R Anurag, LC-ladder filter systematic implementation by OTRA, International Journal Engineering Science and Technology, 19, 4, 1808-1814, 2016
  109. P. Kumar, N. Pandey, S K Paul, Operational Simulation of LC Ladder Filter Using VDTA, Active and Passive Electronic Components, 2017, Article ID 1836727, 8 pages Scopus
  110. V. Bhatia, N. Pandey, Modified Tang’s Current Comparator and Its Application to Full Flash and Two- Step Flash Current Mode ADCs, Journal of Electrical and Computer Engineering, 2017, Article ID 8245181, 12 pages
  111. N. Pandey, D Nand, R. Pandey, Generalised operational floating current conveyor based instrumentation amplifier, IET Circuits, Devices & Systems 10 (3), 209-219,2016 (SCI – 1.297)
  112. N. Pandey, D Nand, VV Kumar, VK Ahalawat, C Malhotra Realization of OFCC based Transimpedance Mode Instrumentation Amplifier, Advances in Electrical and Electronic Engineering 14 (2), 162-167, 2016 Scopus
  113. N. Pandey, D Garg, K. Gupta, B. Choudhary, Hybrid Dynamic MCML Style: A High Speed Dynamic MCML Style, Journal of Engineering, 2016 (2016), Article ID 8027150, 10 pages
  114. N. Pandey, A Mittal, B. Choudhary, K. Gupta, Bus Implementation using New Low Power PFSCL Tri- state buffers, Active and Passive Electronic Components 2017 Article ID 8245181 Scopus
  115. K. Gupta, N. Pandey, M. Gupta, Dynamic Positive-Feedback Source-Coupled Logic (D-PFSCL), International Journal of Electronics, 103, 10, 1626-1638, 2016 (SCI – 1.336)
  116. N. Pandey, R. Pandey, Approach for third order quadrature oscillator realisation, IET Circuits, Devices & Systems 9 (3), 161-171, 2015. (SCI – 1.297)
  117. N. Pandey, P. Kumar, S. K Paul, Voltage differencing transconductance amplifier based resistorless and electronically  tunable  wave  active  filter,  Analog  Integrated  Circuits  and  Signal Processing, 84, pages107–117 (2015) (SCI – 1.337)
  118. N. Pandey, B. Choudhary, Improved tri-state buffer in MOS current mode logic and its application, Analog Integrated Circuits and Signal Processing, 84, 2, 333-340, 2015 (SCI – 1.337)
  119. R. Pal, R. Pandey, N. Pandey, Ramesh Chandra Tiwari, Single CDBA Based Voltage Mode Bistable Multivibrator and Its Applications, Circuits and Systems 6 (11), 237
  120. R. Pandey, N. Pandey, Surabh Chittranshi, S. K Paul, Operational Transresistance Amplifier Based PID Controller, Advances in Electrical and Electronic Engineering 13 (2), 171-181, 2015. Scopus
  121. N. Pandey, K. Gupta, M. Gupta, An efficient triple-tail cell based PFSCL, Microelectronics Journal, 1001-1007, 2014. (SCI – 1.605)
  122. N. Pandey, D. Nand, Z. Khan, Operational floating current conveyor-based single-input multiple-output transadmittance mode filter, Arabian Journal for Science and Engineering 39, 7991–8000, 2014. (SCI- 2.334)
  123. R. Pandey, N. Pandey, R. Mullick, S. Yadav and R. Anurag, All Pass Network based MSO using OTRA, Advances in Electronics, 2015, Article ID 382360, 7 pages
  124. R. Sridhar, N. Pandey, A. Bhattacharyya, V. Bhatia, High Speed High Resolution Current Comparator and its Application to Analog to Digital Converter, J. Inst. Eng. India Ser. B, 97, pages147–154, 2016.
  125. R. Pandey, N. Pandey, G. Komanapalli, R. Anurag, OTRA Based Voltage Mode Third Order Quadrature Oscillator, ISRN Electronics, 2014 , Article ID 126471, 5 pages
  126. N. Pandey, R. Pandey, R. Sridhar, V. Bhatia, A. K. Singh, P. Kumar, CDTA based current mode ADC, International Journal of Advance Research In Science And Engineering http://www.ijarse.com IJARSE, 3, Special Issue (01), 499 -505, 2014
  127. A. Tayal, N. Pandey, R. Pandey, Residue adder based high speed 8-bit Vedic multiplier, International Journal of Electrical and Electronics Engineers No.6, 158 – 162, 2014. Scopus
  128. N. Pandey, K. Gupta, R. Pandey, R. Pandey, T. Mittal, Novel oscillators in subthreshold regime, International Journal of Electrical and Electronics Engineers, 6, 151 – 156, 2014. Scopus
  129. N. Singhal, R. Pandey, N. Pandey, Dual mode biquadratic filter using single VDTA, International Journal of Electrical and Electronics Engineers, 6, 134 – 139, 2014. Scopus
  130. K. Gupta, N. Pandey, M. Gupta, Analysis and design of MOS current mode logic exclusive-OR gate using triple-tail cells, Microelectronics Journal, 44, 6,  561–567, 2013. (SCI – 1.605)
  131. K. Gupta, N. Pandey, M. Gupta, Low-Voltage MOS Current Mode Logic Multiplexer, Radioengineering, 259-268, 2013. (SCI – 0.925)
  132. K. Gupta, N. Pandey, M. Gupta, MCML D-Latch Using Triple-Tail Cells: Analysis and Design, Active and Passive Electronic Components, 2013, Article ID 217674, 9 pages Scopus
  133. M. Bothra, R. Pandey, N. Pandey, S. K. Paul, Operational Trans-Resistance Amplifier Based Tunable Wave Active Filter, Radioengineering, 22, 159 -166, 2013 (SCI – 0.925)
  134. N. Pandey, S. K. Paul, Mixed mode universal filter, J Circuit Syst. Comp., 22, 1, 1250064, 2013.
  135. N. Pandey, P. Kumar, J. Choudhary, Current Controlled Differential Difference Current Conveyor Transconductance Amplifier and Its Application as Wave Active Filter, ISRN Electronics, 2013. Article ID 968749, 11 pages
  136. N. Pandey, S. Arora, R. Takkar, R. Pandey, DVCCCTA-Based Implementation of Mutually Coupled Circuit, ISRN Electronics, 2012. Article ID 303191, 6 pages
  137. N. Pandey, R. Pandey, Current Mode Full-Wave Rectifier Based on a Single MZC-CDTA Active and Passive Electronic Components, 2013 Article ID 967057, 5 pages Scopus
  138. N. Pandey, D. Nand, Z. Khan, Single-Input Four-Output Current Mode Filter Using Operational Floating Current Conveyor, Active and Passive Electronic Components, 2013, Article ID 318560, 8 pages Scopus
  139. N. Pandey, S. Sayal, M. Tripathi, R. Pandey, Realization of S-G Shapers for Detector Readout Front Ends, Elixir Signal Processing 66, 20690-20699, 2014
  140. N. Pandey, V. Bhatia, A. Bhattacharyya, A reference generating inverter-switching-threshold- voltage based current comparator, Journal of Electron Devices, 14, 1100-1103, 2012.
  141. N. Pandey, R. Pandey, S. K. Paul A first order all pass filter and its application in a quadrature oscillator, Journal of Electron Devices, 12, 772-777, 2012.
  142. R. Sridhar, N. Pandey, V. Bhatia, A. Bhattacharyya, New realization of current comparator and its application as current mode ADC, Journal of Electron Devices, 14, 186-1189, 2012.
  143. R. Pandey, N. Pandey, B. Sriram, S. K. Paul, Single OTRA Based Analog Multiplier and Its Applications, ISRN Electronics, 2012, Article ID 890615, 7 pages
  144. R. Pandey, N. Pandey, B. Sriram, S. K. Paul, Single OTRA Based Analog Multiplier and Its Applications, ISRN Electronics 2012. Article ID 890615, 7 pages
  145. R. Pandey, N. Pandey, S. K. Paul Electronically Tunable Transimpedance Instrumentation Amplifier based on OTRA, Journal of Engineering (Hindawi) 2013, Article ID 648540, 5 pages, doi.org/10.1155/2013/648540.
  146. K. Gupta, N. Pandey, M. Gupta, MOS Current Mode Logic with Capacitive Coupling, ISRN Electronics, 2012, Article ID 473257, 7 pages, 2012. doi:10.5402/2012/473257.
  147. K. Gupta, N. Pandey, M. Gupta, Multi-Threshold MOS Current Mode Logic based Asynchronous Pipeline Circuits, ISRN Electronics 2012, Article ID 529194, 7 pages
  148. K. Gupta, N. Pandey, M. Gupta, Low-Power Tri-State Buffer in MOS Current Mode Logic, Analog Integrated Citrcuits and signal processing. April 2013, 75, 1, pp 157-160. (SCI – 1.337)
  149. R. Pandey, S. Chitransi, N. Pandey, C. Shekhar. Single OTRA based PD Controllers, International Journal of Engineering Science and Technology, 4, 1426-1437, 2012.
  150. R. Pandey, N. Pandey, S. K. Paul, A. Singh, B. Sriram, K. Trivedi, Voltage Mode OTRA MOS-C Single Input Multi Output Biquadratic Universal Filter, Advances in Electrical and Electronic Engineering, 10, 337-344, 2012. Scopus
  151. R. Pandey, N. Pandey, S. K. Paul, Voltage Mode Pulse Width Modulator Using Single Operational Transresistance Amplifier, Journal of Engineering, 2013, Article ID 309124, 6 pages, doi.org/10.1155/2013/309124.
  152. R. Pandey, N. Pandey, S. K. Paul, Ajay Singh, B. Sriram, K. Trivedi, Novel grounded inductance simulator using single OTRA, International Journal of Circuit Theory and Application, 42, 10, pages 1069–1079, 2014 (SCI – 2.038)
  153. N. Pandey, S. K. Paul, SIMO Mixed Mode Universal Filter Journal of Active and Passive Electronic Devices, 7, 215-226, 2012.
  154. R. Pandey, N. Pandey, T. Negi, V. Garg, CDBA Based Universal Inverse Filter, ISRN Electronics, 2013, Article ID 181869, 6 pages
  155. R. Pandey, N. Pandey, S. K. Paul, K. Anand, K. G. Gautam, Voltage Mode Astable Multivibrator Using Single CDBA, ISRN Electronics, , 2013, Article ID 390160, 8 pages
  156. N. Pandey, P. Kumar, Realization of Resistorless Wave Active Filter using Differential Voltage Current Controlled Conveyor Transconductance Amplifier, Radioengineering, 20, 911-916, 2011 (SCI – 0.925)
  157. N. Pandey, S. K. Paul, Differential Difference Current Conveyor Transconductance Amplifier: A New Analog Building Block for Signal Processing, Journal of Electrical and Computer Engineering, 2011, Article ID 361384, 10 pages Scopus
  158. N. Pandey, S. K. Paul, Single CDTA-Based Current Mode All-Pass Filter and Its Applications, Journal of Electrical and Computer Engineering 2011, Article ID 897631, 5 pages Scopus
  159. K. Gupta, R. Sridhar, J. Chaudhary, N. Pandey, M. Gupta, New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic, Journal of Electrical and Computer Engineering 2011, Article ID 670508, 6 pages Scopus
  160. N. Pandey, P. Kumar, Differential voltage current conveyor transconductance amplifier based wave active filter Journal of Electron Devices, 10, 429-432, 2011.
  161. N. Pandey, R. Bazaz, R. Manocha MO-CCCCTA-Based Floating Positive and Negative Inductors and Their Applications, Journal of Electrical and Computer Engineering 2011, Article ID 150354, 8 pages, Scopus
  162. R. Pandey, N. Pandey, S. K. Paul, A. Singh, B. Sriram, K. Trivedi, New Topologies of Lossless Grounded Inductor Using OTRA, Journal of Electrical and Computer Engineering, 2011, Article ID 175130, 6 pages Scopus
  163. R. Pandey, N. Pandey, M. Bothra, S. K. Paul, Operational Transresistance Amplifier-Based Multiphase Sinusoidal Oscillators, Journal of Electrical and Computer Engineering , 2011. Article ID 586853, 8 pages Scopus
  164. N. Pandey and S. K Paul, VM and CM Universal Filters Based on single DVCCTA, Active and Passive Electronic Component 2011, Article ID 929507, 7 pages. Scopus
  165. S. K. Paul, N. Pandey, A novel current mode channel select filter for multi standard wireless receiver, Journal of Active and Passive Electronic Devices, 6 , 327-332, , 2011.
  166. K. Gupta, N. Pandey, M. Gupta, A new active shunt-peaked MCML based high performance 1:8 demultiplexer for serial communication, International Journal of Engineering Science and Technology, 2, 4632-4639, 2010.
  167. V. Bhatia, N. Pandey and A. Bhattacharyya, Application based comparison of different analog to digital converter architectures, International Journal of Engineering Science and Technology, 2, 3396-3404, 2010.
  168. V. Bhatia, N. Pandey and A. Bhattacharyya, A 4-bit expandable current mode ADC based on different current comparator architectures, International Journal of Engineering Science and Technology, 2, 7380-7384, 2010.
  169. R. Pandey N. Pandey, R. Anurag, Voltage Reference Circuits: A Classification, International Journal of Engineering Science and Technology, 2, 4929-4935, 2010.
  170. N. Pandey, S. K. Paul, A. Bhattachryya, Realization of Generalized Mixed Mode Universal Filter Using CCCIIs, Journal of Active and Passive Electronic Devices, 5, 279 -293, 2010.
  171. N. Pandey, S. K. Paul, Digitally Switched Current Mode Universal Filter, Journal of Active and Passive Electronic Devices, 5, 197-208, 2010.
  172. N. Pandey, S. K. Paul, SIMO Transadmittance mode Active - C Universal Filter, Circuit and Systems, 1, 54 - 58, 2010.
  173. N. Pandey, S. K. Paul, S. B. Jain, Voltage Mode Tow Thomas Universal Filter: A Current Controlled Conveyor Approach, Journal of Active and Passive Electronic Devices, 5, 105 -113, 2010.
  174. N. Pandey, S. K. Paul, A. Bhattachryya, Realization of Generalized Mixed Mode Universal Filter Using CCCIIs, Journal of Active and Passive Electronic Devices, 5, 279 -293, 2010.
  175. N. Pandey, S. K. Paul and S. B. Jain, A new electronically tunable current mode universal filter using MO-CCCII, Analog Integrated Circuits for Signal Processing, 58, 171-178, 2009. (SCI – 1.337)
  176. N. Pandey, S. K. Paul, S. B. Jain, New High-Input Impedance Voltage-Mode Universal Biquad: Multi Input Multi Output, Journal of Active and Passive Electronic Devices, 3, 93-100, 2008.
  177. N. Pandey, S. K. Paul, S. B. Jain, Voltage Mode Universal Filter using Two Plus Type CCIIs, Journal of Active and Passive Electronic Devices, 3, 165-173, 2008.
  178. N. Pandey and S. K. Paul, A Novel Electronically Tunable Sinusoidal Oscillator Based on CCCII(IR), Journal of Active and Passive Electronic Devices, 3, 134-141, 2008.
  179. N. Pandey, S. K. Paul, A. Bhattacharyya, S. B. Jain, Insensitive Mixed Mode Biquad Using Reduced Number of Active and Passive Components, Journal of Active and Passive Electronic Devices, 2, 117- 125, 2007.
  180. N. Pandey, S. K. Paul, Ashok Bhattacharyya and S.B. Jain, A new mixed mode biquad using reduced number of active and passive elements, IEICE Electronics Express, 3, 6, 115-121, 2006. (SCI- 0.578)
  181. N. Pandey and S. K. Paul, Multi-input Single-output Universal Current Mode Biquad, Journal of Active and Passive Electronic Devices, 1, 229-240, 2006.
  182. N. Pandey, S. K. Paul, Ashok Bhattacharyya and S.B. Jain, A novel current controlled current mode universal filter: SITO approach, IEICE Electronics Express, 2, 17, 451-457, 2005. (SCI- 0.578)
  183. N. Pandey and S. K. Paul, All Pass filter based on CCII- and CCCII-, Int. Journal of Electronics, 91, 485- 489, 2004. (SCI – 1.336)

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