• Paper titled “Plagiarism Detection in Polyphonic Music using Monaural Signal Separation” has been selected for publication and poster presentation in INTERSPEECH-2012 conference  held in September  9-13,2012|Portland,Oregon.
• Paper titled “Comparison of Time Series Similarity Measures for Plagiarism Detection in Music” was selected for poster presentation and publication in INDICON 2015 12th IEEE India International conference held in Dec 17-20, 2015 | Jamia Millia Islamia , New Delhi.
• Paper titled “Hardware Design of Dynamic Time Warping Algorithm based on FPGA in Verilog” has been published online in International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE), Vol.4, Issue 2, February 2015.
• Paper titled “Hardware Design of Similarity Measures for Time Series based on FPGA in Verilog” has been selected for publication in 2^nd International Conference on “VLSI, Communication and Networks (VCAN-2015)”, April 18-19,2015| Alwar (Rajasthan).
• Book Chapter titled “Novel hardware design of correlation function and its application on binary matrix factorization based features” was selected for oral presentation in International Conference on Artificial Intelligence: Advances and Applications (ICAIAA-2019) (28-29th June 2019) Organized by RTU, Kota, Poornima College of Engineering, Poornima Institute of Engineering & Technology, Jaipur and JNTU Hyderabad, eBook ISBN: 978-981-15-1059-5, Hardcover ISBN: 978-981-15-1058-8, Series ISSN :2524-7565, DOI: 10.1007/978-981-15-1059-5, Publisher: Springer Singapore.
• Book Chapter titled “NOVEL FPGA BASED HARDWARE DESIGN OF CANONICAL SIGNED DIGIT MATRIX MULTIPLIER AND ITS COMPARATIVE ANALYSIS WITH OTHER MULTIPLIERS” published in proceedings of ICAIAA 2019 in International Conference on Artificial Intelligence: Advances and Applications (ICAIAA-2019) (28-29th June 2019) Organized by RTU, Kota, Poornima College of Engineering, Poornima Institute of Engineering & Technology, Jaipur and JNTU Hyderabad, eBook ISBN: 978-981-15-1059-5, Hardcover ISBN: 978-981-15-1058-8, Series ISSN :2524-7565, DOI: 10.1007/978-981-15-1059-5, Publisher: Springer Singapore.
• P. Garg and K. Suneja, "Hardware design of high speed 1-D DCT module using approximate floating point adder," 2020 7th International Conference on Signal Processing and Integrated Networks (SPIN), Noida, India, 2020, pp. 623-625.
• M. Yadav, R. Koul and K. Suneja, "FPGA Based Hardware Design of PCA for Face Recognition," 2020 7th International Conference on Signal Processing and Integrated Networks (SPIN), Noida, India, 2020, pp. 642-646.
• A. Gupta and K. Suneja, "Hardware Design of Approximate Matrix Multiplier based on FPGA in Verilog," 2020 4th International Conference on Intelligent Computing and Control Systems (ICICCS), Madurai, India, 2020, pp. 496-498, doi: 10.1109/ICICCS48265.2020.9121004. Publisher: IEEE.
• B. Mohindroo, A. Paliwal and K. Suneja, "FPGA based Faster Implementation of MAC Unit in Residual Number System," 2020 International Conference for Emerging Technology (INCET), Belgaum, India, 2020, pp. 1-4, doi: 10.1109/INCET49848.2020.9154105. Publisher:IEEE
• R. Koul, M. Yadav and K. Suneja, "Comparative Analysis of FPGA Based Hardware Design of Dynamic Time Warping Algorithm using Different Multiplier Architectures," 2020 IEEE International Conference on Computing, Power and Communication Technologies (GUCON), Greater Noida, India, 2020, pp. 599-603, doi: 10.1109/GUCON48875.2020.9231244.
• Jain M., Saini R., Manish, Suneja K. (2020) Novel Hardware Design of Correlation Function and Its Application on Binary Matrix Factorization Based Features. In: Mathur G., Sharma H., Bundele M., Dey N., Paprzycki M. (eds) International Conference on Artificial Intelligence: Advances and Applications 2019. Algorithms for Intelligent Systems. Springer, Singapore. https://doi.org/10.1007/978-981-15-1059-5_13.
• A. Negi, D. Saxena and K. Suneja, "High Level Synthesis of Chaos based Text Encryption Using Modified Hill Cipher Algorithm," 2020 IEEE 17th India Council International Conference (INDICON), New Delhi, India, 2020, pp. 1-5, doi: 10.1109/INDICON49873.2020.9342591.
• A. Paliwal, B. Mohindroo and K. Suneja, "Hardware Design of Image Encryption and Decryption Using CORDIC Based Chaotic Generator," 2020 5th IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE), Jaipur, India, 2020, pp. 1-5, doi: 10.1109/ICRAIE51050.2020.9358354.
• A. Garg, B. Yadav, K. Sahu and K. Suneja, "An FPGA based Real time Implementation of Nosé hoover Chaotic System using different numerical Techniques," 2021 7th International Conference on Advanced Computing and Communication Systems (ICACCS), 2021, pp. 108-113, doi: 10.1109/ICACCS51430.2021.9441923.
• A. Kumar, A. Ansari, A. Srivastava and K. Suneja, "Fast Approximate Matrix Multiplier based on Dadda Reduction and Carry Save Ahead Adder," 2021 7th International Conference on Advanced Computing and Communication Systems (ICACCS), 2021, pp. 1058-1061, doi: 10.1109/ICACCS51430.2021.9441960.
• Negi A., Saxena D., Kunal, Suneja K. (2022) An Anatomization of FPGA-Based Neural Networks. In: Nayak P., Pal S., Peng SL. (eds) IoT and Analytics for Sensor Networks. Lecture Notes in Networks and Systems, vol 244. Springer, Singapore. https://doi.org/10.1007/978-981-16-2919-8_45.
• A. Kumar, M. Kumar, G. S. Jha and K. Suneja, "FPGA based design of multifunction ALU," 2021 Fourth International Conference on Computational Intelligence and Communication Technologies (CCICT), 2021, pp. 72-76, doi: 10.1109/CCICT53244.2021.00025.
• Suneja, Kriti & Pandey, Neeta & Pandey, Rajeshwari. (2022). Systematic Realization of CFOA Based Rössler Chaotic System and Its Applications. Arabian Journal for Science and Engineering. 10.1007/s13369-021-06379-9. 
• A. Chaudhary, A. Kumar, A. Srivastava and K. Suneja, "FPGA-based Pipelined LSTM accelerator with Approximate matrix multiplication technique," 2021 5th International Conference on Electrical, Electronics, Communication, Computer Technologies and Optimization Techniques (ICEECCOT), 2021, pp. 438-442, doi: 10.1109/ICEECCOT52851.2021.9707941.
• K. Suneja, N. Pandey and R. Pandey, "OTRA based Design of Chaotic Systems with One and Two Non-Linearities," 2022 International Conference for Advancement in Technology (ICONAT), 2022, pp. 1-5, doi: 10.1109/ICONAT53423.2022.9726005.
• B. Yadav, A. Garg, K. Sahu and K. Suneja, "A Real Time FPGA Implementation and Analysis of a Novel Chaotic System," 2022 International Conference for Advancement in Technology (ICONAT), 2022, pp. 1-4, doi: 10.1109/ICONAT53423.2022.9725976.
• K. Suneja, A. Chaudhary, A. Kumar and A. Srivastava, "Recent Advancements in FPGA-based LSTM Accelerator," 2022 International Conference for Advancement in Technology (ICONAT), 2022, pp. 1-5, doi: 10.1109/ICONAT53423.2022.9726002.
• Suneja, Kriti & Pandey, Neeta & Pandey, Rajeshwari. (2022). Novel Pehlivan–Uyarŏglu Chaotic System Variants and their CFOA Based Realization. Journal of Circuits, Systems and Computers. 10.1142/S0218126622501717. 
• K. Suneja, N. Pandey and R. Pandey, "Realization of Chua’s circuit using VDBA based nonlinear resistor and inductor simulator," 2022 International Mobile and Embedded Technology Conference (MECON), Noida, India, 2022, pp. 367-371, doi: 10.1109/MECON53876.2022.9751973.
• K. Suneja, N. Pandey and R. Pandey, "Circuit realization of chaotic systems with quadratic nonlinearity using AD633 based generic topology," 2022 International Conference on Computing, Communication, and Intelligent Systems (ICCCIS), Greater Noida, India, 2022, pp. 284-289, doi: 10.1109/ICCCIS56430.2022.10037747.
• S. Suchit and K. Suneja, "Implementation of Secure Communication System Using Chaotic Masking," 2022 IEEE Global Conference on Computing, Power and Communication Technologies (GlobConPT), New Delhi, India, 2022, pp. 1-5, doi: 10.1109/GlobConPT57482.2022.9938303.
• Suneja, K., Garg, A., Yadav, B., Sahu, K. (2023). Analysis of Adaptive Control Synchronization of Nosé–Hoover Chaotic System. In: Senjyu, T., So-In, C., Joshi, A. (eds) Smart Trends in Computing and Communications. SmartCom 2023. Lecture Notes in Networks and Systems, vol 650. Springer, Singapore. https://doi.org/10.1007/978-981-99-0838-7_33.
• K Suneja, N Pandey, R Pandey, “A Novel Chaotic System with Exponential Nonlinearity and its Adaptive Self-Synchronization: From Numerical Simulations to Circuit Implementation,” Journal of Circuits, Systems and Computers, 2350296.
• K. Suneja, B. Kumar, K. Jha and L. S. Chuphal, "Image Encryption Using Novel Chaotic System," 2024 3rd International Conference for Innovation in Technology (INOCON), Bangalore, India, 2024, pp. 1-4, doi: 10.1109/INOCON60754.2024.10511693.
• Suneja, K., Pandey, N. & Pandey, R. Novel four dimensional hyperchaotic system: analysis, adaptive control, analog and digital circuit design. Int. j. inf. tecnol. 17, 1137–1145 (2025). https://doi.org/10.1007/s41870-024-02335-6

Conferences/ Workshops/ Seminars attended:

Participated in an AICTE Sponsored Short Term Course on “ Phase- Locked Loops” organized by Department of Electrical Engineering, Indian Institute of Technology MADRAS  from 17^th December to 22^nd December, 2018.

Attended Faculty Induction Programme (17^th June, 19 to 16^th July,19) supported by Ministry of Human Resource Development under the scheme Pandit Madan Mohan Malaviya National Mission on Teacher and Training organized by Mahatma Hansraj Faculty Development Centre at Hansraj College, University of Delhi, Delhi-110007.

Successfully completed the Internship Program on Functional Verification using SystemVerilog held from 30th November to 29th December 2021, from Sandeepani School of Embedded System Design, Bangalore.

Successfully completed the AICTE-ISTE approved Orientation/ Refresher programme on " Recent Advancement in ML & AI" held from 16-12-2021 to 22-12-2021 organized by Bharati Vidyapeeth's College of Engineering, Paschim Vihar, New Delhi.

Presented paper entitled " OTRA based design of chaotic systems with one and two non-linearities" in 2022 International Conference for Advancement in Technology (ICONAT) during 21st and 22nd January, 2022.

Participated as Technical Committee Member (TPC) in the IEEE IAS 5th IEEE International Conference on Computing, Power and Communication Technologies (GUCON-2022) which to be held during September 23-25, 2022 , at India Habitat Centre, Lodhi Road, New Delhi, India.

Participated in the one-week Online Short Term Course on "DEMYSTIFYING INTELLECTUAL PROPERTY FOR RESEARCH INTEGRITY AND ECONOMIC DEVELOPMENT" organized by the Department of Computer Science & Engineering, Delhi Technological University, Delhi held from March 13 to 17, 2023.

Presenter of the paper titled FPGA based design of chaotic systems with quadratic non-linearities presented at the 4th International Conference on Data Analytics and Management (ICDAM-2023), organized jointly by London Metropolitan University, London, UK in association with the Karkonosze University of Applied Sciences, Jelenia Gora, Poland, Europe, Politécnico de Portalegre, Portugal, Europe and BPIT, GGSIPU, Delhi on 23rd – 24th June 2023.

Reviewed conference papers for 15th International IEEE Conference on Computing Communication and Networking Technologies, IIT - Mandi, India, June 24,-28, 2024.

Reviewed conference papers for the 3rd International Conference on Power Electronics, Intelligent Control, and Energy Systems (IEEE-ICPEICES-2024), DTU, Delhi, 26th to 28th of April, 2024.

 

Summer institutes, refresher or orientation courses attended or conducted

Successfully completed the AICTE- ISTE approved Orientation/ Refresher Programme on “Recent Advancement in ML and AI” held during 16-12-2021 to 22-12-2021 organized by Bharati Vidyapeeth’s College of Engineering, Paschim Vihar, New Delhi.

Attended one week Faculty Development Program on “Advancement and Challenges in VLSI Design and Nanoscale Devices” from 27th May, 24 to 31st May, 24 organized by Dept. of ECE, DTU.

Attended one week Faculty Development Program on “ Next Generation Wireless Networks” from 12th Dec, 23 to 16th Dec, 23 organized by Dept. of ECE, DTU.

Conducted one week workshop on “Digital System Design using EDA Tools” from 10th June, 24 to 14th June, 24 for students of DTU.

Attended 2 weeks Industrial Training on Cyber security and networking organized by ALTTC, Ghaziabad from 6th July to 22nd July, 2023.

Conferences Organized:

Organized “International Conference on Signal Processing, VLSI and Communication Engineering (ICSPVCE-2019)” in capacity of a member, organizing committee, at Department of Electronics and Communication Engineering, DTU, Delhi, during March 28^th-30^th, 2019.

Certification courses:

• Successfully completed AI For Everyone, an online non-credit course authorized by deeplearning.ai and offered through Coursera.
• Successfully completed Diabetes – the Essential Facts, an online non-credit course authorized by University of Copenhagen and offered through Coursera.

Successfully completed 12-week NPTEL Online certification course (3 or 4 credits) on “ VLSI Physical Design with Timing Analysis” with a consolidated score of 64%.

Guest Lectures:

Delivered an expert lecture on “ Basics of VHDL for digital design” in TEQIP III SPONSORED ONE WEEK STAFF DEVELOPMENT PROGRAM ON ELECTRONIC DESIGN AUTOMATION AND DOCUMENTATION TOOLS on July 26, 2019

Students working on academic projects under my guidance: