Room No. FW1-SF1A, Department of Electrical Engineering, Delhi Technological University, Bawana Road, Shahbad Daulatpur, Delhi-110042, India.

Professional Experience:

• Assistant Professor, Department of Electrical Engineering, Delhi Technological University, Delhi, India (Jan. 2020 – Present)
• Assistant Professor in Dept. of Electrical and Electronics Engineering, BITS Pilani, Goa Campus, Goa, India (Dec. 2019 to Jan 2020)
• Research Associate in Dept. of Electronics and Communication Engineering, IIT, Roorkee, Uttarakhand, India (Jul. 2019 to Oct. 2019)
• Assistant Professor in Dept. of Electronics and Communication Engineering, College of Engineering Roorkee (COER), Roorkee, Uttarakhand, India from (Aug. 2011 to Jun. 2014)

Publications

Journals/Transactions:

• Chaudhry Indra Kumar, and Bulusu Anand, "A Highly Reliable and Energy Efficient Radiation Hardened 12T SRAM Cell Design", in IEEE Transactions on Device and Material reliability, 2020.
• Chaudhry Indra Kumar, and Bulusu Anand, "A Highly Reliable and Energy Efficient Triple-Node-Upset Tolerant Latch Design", in IEEE Transactions on Nuclear Science, 2019.
• Chaudhry Indra Kumar, I. Bhatia, A. K. Sharma, D. Shegal, H. S. Jatana, and Bulusu Anand, " A Physics based Variability Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage Latches", in IEEE Transactions on Very large Scale Integration, 2019.
• Chaudhry Indra Kumar, A. K. Sharma, Rajendra Pratap and Bulusu Anand, "An energy-efficient variation aware self-correcting latch", in Elsevier Microelectronics Journal, 2019.
• Chaudhry Indra Kumar, and Bulusu Anand, "High Performance Energy Efficient Radiation Hardened Latch for Low Voltage Applications", in Elsevier Integration, the VLSI Journal, 2019.
• Chaudhry Indra Kumar, and Bulusu Anand, "Design of highly reliable energy-efficient SEU tolerant 10T SRAM cell", in IET Electronics Letters, 2018.
• Chaudhry Indra Kumar, and Bulusu Anand, "A Highly Reliable Energy Efficient Double Node Upset Tolerant Latch", in Elsevier Integration, the VLSI Journal. (Under review).

Conferences:

• Chaudhry Indra Kumar, A Single Node Upset Hardened Latch Design in NTV Regime in IEEE GUCON, 2021.
• A Gosh, M. Saif, Chaudhry Indra Kumar, “Time-Borrowing Flip-Flop Architecture for Multi-Stage Timing Error Resilience in DVFS Processors” in IEEE CONIT 2021.
• Chaudhry Indra Kumar, and Bulusu Anand, "Design and Analysis of Energy Efficient Self Correcting Latches considering Metastability", in IEEE PRIME, 2018.
• Chaudhry Indra Kumar, A. K. Sharma, S. Miryala, and Bulusu Anand, " A novel energy-efficient self-correcting methodology employing INWE", in IEEE SMACD, 2016.
• S. Parashar, Chaudhry Indra Kumar and M. Pattanaik “An Efficient Design Technique for High Performance Dynamic Feed-through Logic with Enhanced Noise Tolerance” IEEE ISVLSI, 2011.
• M. Pattnaik, S. Parashar, V. Mahor, Chaudhry Indra Kumar and A. Chouhan, “A Novel Low Power noise tolerant High Performance Dynamic Feedthrough Logic Design Technique” in IEEE ISED, 2011.

Courses Taught/Teaching at DTU

A. Theory

• Digital VLSI Design (B. Tech.)
• Antenna and Wave Propagation (B. Tech.)
• Linear integrated Circuits (B.Tech.)
• Analog Electronics (B. Tech.)
• Digital Signal processing (B.Tech.)
• Electromagnetic Filed Theory (B.Tech.)
• Microprocessor and Microcontroller (B. Tech.)

B. Laboratory 

• Analog Electronics Laboratory (B.Tech.)
• Electronic Devices and Circuit Laboratory (B.Tech.)
• Linear Integrated Circuits Laboratory (B.Tech.)
• Microprocessor and Microcontroller Laboratory (B.Tech.)
• Digital Signal Processing Laboratory (B.Tech.)
• Basic Electrical Engineering Laboratory (B. Tech)